Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-28 13:05 |
Kumamoto |
(Primary: On-site, Secondary: Online) |
Development of ASIC Prototype Chip Evaluation System using FPGA-SoM Masashi Imai (Hirosaki Univ.), Kenji Kise (Tokyo Tech.), Tomohiro Yoneda (NII) VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42 |
An ASIC prototype chip requires the corresponding evaluation system based on its specification, resulting in lack of ver... [more] |
VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42 pp.1-6 |
RECONF |
2020-09-10 16:30 |
Online |
Online |
An implementation of an object detection algorhythm on Vitis AI and Winning a prize in the 2nd AI Edge Katsunoshin Matsui, Hiromu Miyazaki, Kazuki Nakano, Kenji Kise (Tokyo Tech) RECONF2020-23 |
(To be available after the conference date) [more] |
RECONF2020-23 pp.25-29 |
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] |
2020-01-23 13:30 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
Design and implementation of a RISC-V computer system running Linux in Verilog HDL Junya Miura, Hiromu Miyazaki, Kenji Kise (Tokyo Tech) VLD2019-72 CPSY2019-70 RECONF2019-62 |
RISC-V is an instruction set architecture developed at the University of California, Berkeley.
Processors using RISC-V ... [more] |
VLD2019-72 CPSY2019-70 RECONF2019-62 pp.117-122 |
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] |
2020-01-23 13:55 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
Design and implementation of a RISC-V soft processor adopting five-stage pipelining Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise (Tokyo Tech) VLD2019-73 CPSY2019-71 RECONF2019-63 |
In this paper, we propose a RISC-V soft processor adopting five-stage pipelining optimized for FPGAs that support RV32I,... [more] |
VLD2019-73 CPSY2019-71 RECONF2019-63 pp.123-128 |
RECONF |
2019-05-09 12:35 |
Tokyo |
Tokyo Tech Front |
Efficient Instruction Fetch Architectures for a RISC-V Soft Processor Hiromu Miyazaki, Junya Miura, Kenji Kise (Tokyo Tech) RECONF2019-1 |
We aim to develop a cost-effective RISC-V scalar processor of pipelining for FPGAs. In this report, we try to implement ... [more] |
RECONF2019-1 pp.1-6 |
RECONF |
2018-05-25 13:00 |
Tokyo |
GATE CITY OHSAKI |
[Invited Talk]
Kenji Kise (Titech) RECONF2018-14 |
[more] |
RECONF2018-14 p.71 |
CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] |
2017-01-24 17:45 |
Kanagawa |
Hiyoshi Campus, Keio Univ. |
Trace-Driven Emulation of Large-Scale Networks-on-Chip on FPGAs Thiem Van Chu, Kenji Kise (Tokyo Tech) VLD2016-93 CPSY2016-129 RECONF2016-74 |
[more] |
VLD2016-93 CPSY2016-129 RECONF2016-74 pp.153-158 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 15:05 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus |
A Novel Merge Network for FPGA Sorting Accelerators Makoto Saitoh, Susumu Mashimo, Thiem Van Chu, Kenji Kise (Tokyotech) RECONF2016-42 |
[more] |
RECONF2016-42 pp.13-18 |
CPSY, DC, IPSJ-ARC (Joint) [detail] |
2016-08-09 15:00 |
Nagano |
Kissei-Bunka-Hall (Matsumoto) |
A Fast Emulation System for Fat-Tree-Based Network-on-Chips Thiem Van Chu, Kenji Kise (Tokyo Tech) CPSY2016-24 |
(To be available after the conference date) [more] |
CPSY2016-24 pp.161-166 |
RECONF |
2015-06-19 16:25 |
Kyoto |
Kyoto University |
Towards the Fastest FPGA-based Sorting Hardware in the World Ryohei Kobayashi, Kenji Kise (Tokyo Tech) RECONF2015-12 |
Sorting is an extremely important computation kernel that has been accelerated by using FPGAs in a lot of fields, such a... [more] |
RECONF2015-12 pp.65-70 |
DC, CPSY |
2015-04-17 10:50 |
Tokyo |
|
Design and Implementation of FPGA-based Sorting Accelerator Ryohei Kobayashi, Kenji Kise (Tokyo Tech) CPSY2015-5 DC2015-5 |
Sorting is an extremely important computation kernel that has been tried to be accelerated in a lot of fields, such as d... [more] |
CPSY2015-5 DC2015-5 pp.25-30 |
RECONF, CPSY, VLD, IPSJ-SLDM [detail] |
2015-01-30 14:55 |
Kanagawa |
Hiyoshi Campus, Keio University |
Design and Implementation of Portable and High-speed FPGA Accelerator employing USB3.0 Takuma Usui, Ryohei Kobayashi, Kenji Kise (Tokyo Tech) VLD2014-145 CPSY2014-154 RECONF2014-78 |
FPGA accelerators can obtain higher computation performance and better power efficiency than CPUs and GPUs, because desi... [more] |
VLD2014-145 CPSY2014-154 RECONF2014-78 pp.205-210 |
RECONF, CPSY, VLD, IPSJ-SLDM [detail] |
2015-01-30 15:15 |
Kanagawa |
Hiyoshi Campus, Keio University |
MieruSys Project : Developing an Advanced Computer System with Multiple FPGAs Yuki Matsuda, Eri Ogawa, Tomohiro Misono (Tokyo Tech), Naoki Fujieda, Shuichi Ichikawa (TUT), Kenji Kise (Tokyo Tech) VLD2014-146 CPSY2014-155 RECONF2014-79 |
This paper describes the design and current development of MieruSys project which develops a future computer system with... [more] |
VLD2014-146 CPSY2014-155 RECONF2014-79 pp.211-216 |
RECONF |
2014-09-18 15:45 |
Hiroshima |
|
Challenge for Ultrafast 10K-Node NoC emulation on FPGA Thiem Van Chu, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) RECONF2014-21 |
With thousands of cores in the near future NoC architectures, the simulation time is a serious problem that makes archit... [more] |
RECONF2014-21 pp.23-28 |
CPSY, DC (Joint) |
2014-07-29 09:25 |
Niigata |
Toki Messe, Niigata |
Design and Performance Evaluation of a Manycore Processor for Large FPGA Haruka Mori, Kenji Kise (Tokyo Tech) CPSY2014-18 |
Due to the limitations of the single-threaded performance and
the improvement of semiconductor technology,
manycore pr... [more] |
CPSY2014-18 pp.49-54 |
CPSY |
2013-10-03 10:45 |
Chiba |
Makuhari Messe |
Design of a translator to Verilog HDL from hardware modeling language ArchHDL Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) CPSY2013-31 |
We have proposed ArchHDL as a new language for hardware RTL modeling. In ArchHDL, we realized continuous assignment and ... [more] |
CPSY2013-31 pp.1-6 |
CPSY |
2013-10-03 11:10 |
Chiba |
Makuhari Messe |
TMR execution on SmartCore system for dependable many-core processors Ryosuke Sasakawa, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) CPSY2013-32 |
In order to improve the chip-level dependability, we have proposed SmartCore system, NoC-based DMR(Dual Modular Redundan... [more] |
CPSY2013-32 pp.7-12 |
RECONF |
2013-09-19 14:15 |
Ishikawa |
Japan Advanced Institute of Science and Technology |
Development of Memory Management Framework for FPGA-based Prototyping Shinya Takamaeda-Yamazaki (Tokyo Inst. of Tech./JSPS Research Fellow), Kenji Kise (Tokyo Inst. of Tech.) RECONF2013-35 |
FPGA-based rapid prototyping supports faster emulation, but it requires the detailed implementation for each FPGA charac... [more] |
RECONF2013-35 pp.91-96 |
CPSY, VLD, RECONF, IPSJ-SLDM [detail] |
2013-01-17 15:15 |
Kanagawa |
|
Design and Implementation of High Performance Stencil Computer by using Mesh Connected FPGA Arrays Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) VLD2012-134 CPSY2012-83 RECONF2012-88 |
We develop an effective stencil computation accelerator by using multiple FPGAs, which employs 2D-mesh architecture conn... [more] |
VLD2012-134 CPSY2012-83 RECONF2012-88 pp.159-164 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:25 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
Rethinking virtual channel usage in network-on-chip Ryosuke Sasakawa, Naoki Fujieda, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) CPSY2012-51 |
An important requirement of routing algorithm is the freedom from deadlock in Network-on-Chip (NoC).For generating deadl... [more] |
CPSY2012-51 pp.21-26 |