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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SDM |
2015-03-02 10:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg |
[Invited Talk]
Integration Technology of 3D FPGA with Performance Scalability and Function Flexibility Kenichi Takeda, Mayu Aoki (Hitachi) SDM2014-163 |
Three-layer stacked wafer with CMOS devices was demonstrated by using hybrid wafer bonding and via-last through silicon ... [more] |
SDM2014-163 pp.7-11 |
SDM |
2014-01-29 15:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
3D Integrated CMOS Device by Using Wafer Stacking and Via-last TSV Mayu Aoki, Futoshi Furuta, Kazuyuki Hozawa, Yuko Hanaoka, Kenichi Takeda (Hitachi) SDM2013-145 |
A three-layer-stacked wafer with CMOS devices was fabricated for the first time by using hybrid wafer bonding and backsi... [more] |
SDM2013-145 pp.43-46 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:00 |
Kagoshima |
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[Invited Talk]
Circuit design for 3D-stacking using TSV interconnects Kenichi Osada, Futoshi Furuta, Kenichi Takeda (Hitachi) VLD2013-73 CPM2013-117 ICD2013-94 CPSY2013-58 DC2013-39 RECONF2013-41 |
To improve the performance of 3D-stacking using TSV interconnects, circuit techniques were developed. To improve Z-axis ... [more] |
VLD2013-73 CPM2013-117 ICD2013-94 CPSY2013-58 DC2013-39 RECONF2013-41 pp.93-96(VLD), pp.55-58(CPM), pp.55-58(ICD), pp.1-4(CPSY), pp.93-96(DC), pp.13-16(RECONF) |
SDM |
2010-02-05 16:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Evaluation of Line-Edge Roughness in Cu/Low-k Interconnect Patterns Atsuko Yamaguchi, D. Ryuzaki, Kenichi Takeda (Hitachi), Hiroki Kawada (Hitachi High-Tech.) SDM2009-192 |
To establish the method for evaluating Cu/low-k interconnect line-edge roughness (LER), resist, low-k, and Cu/low-k samp... [more] |
SDM2009-192 pp.59-63 |
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