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 Results 1 - 12 of 12  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-27
14:00
Kagoshima   [Invited Talk] Circuit design for 3D-stacking using TSV interconnects
Kenichi Osada, Futoshi Furuta, Kenichi Takeda (Hitachi) VLD2013-73 CPM2013-117 ICD2013-94 CPSY2013-58 DC2013-39 RECONF2013-41
To improve the performance of 3D-stacking using TSV interconnects, circuit techniques were developed. To improve Z-axis ... [more] VLD2013-73 CPM2013-117 ICD2013-94 CPSY2013-58 DC2013-39 RECONF2013-41
pp.93-96(VLD), pp.55-58(CPM), pp.55-58(ICD), pp.1-4(CPSY), pp.93-96(DC), pp.13-16(RECONF)
NLP, CAS 2012-09-21
13:10
Kochi Eikokuji Campus, University of Kochi [Invited Talk] Fully digital voltage-mode control based on predictive hysteresis method (FDVC-PH) for DC-DC converters
Ming Liu, Tatsuo Nakagawa, Kenichi Osada (Hitachi) CAS2012-44 NLP2012-70
 [more] CAS2012-44 NLP2012-70
pp.75-80
SDM 2011-10-21
15:50
Miyagi Tohoku Univ. (Niche) Performance Evaluation of 3D FPGA using Through Silicon Via
Naoto Miyamoto (Tohoku Univ.), Yohei Matsumoto (Tokyo Univ. of Marine Science and Technology), Hanpei Koike (AIST), Tadayuki Matsumura, Kenichi Osada, Yahoko Nakagawa (ASET), Tadahiro Ohmi (Tohoku Univ.) SDM2011-113
3D LSI fabrication is a promising technology as a representative of “More Than Moore” stream. 3D FPGA is one of the kill... [more] SDM2011-113
pp.91-96
ICD, IPSJ-ARC 2011-01-20
11:00
Kanagawa Keio University (Hiyoshi Campus) Performance Evaluation of 3D FPGA with Homogeneous Tileable Structure
Naoto Miyamoto (Tohoku Univ.), Hanpei Koike (AIST), Yohei Matsumoto (Kaiyo Univ.), Tadayuki Matsumura, Kenichi Osada, Yahoko Nakagawa, Keisuke Toyama (ASET), Tadahiro Ohmi (Tohoku Univ.)
3D LSI fabrication is a promising technology as a representative of "More Than Moore" stream. 3D FPGA is one of the kill... [more] ICD2010-130
pp.13-18
VLD, IPSJ-SLDM 2010-05-20
10:00
Fukuoka Kitakyushu International Conference Center 3D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link
Makoto Saen, Kenichi Osada, Yasuyuki Okuma (Hitachi), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Itaru Nonomura (Renesas Technology), Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Tadahiro Kuroda (Keio Univ.) VLD2010-5
This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chi... [more] VLD2010-5
pp.43-47
ICD 2010-04-22
11:15
Kanagawa Shonan Institute of Tech. A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation
Shigenobu Komatsu, Masanao Yamaoka (HITACHI), Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki (Renesas Technology Corp.), Kenichi Osada (HITACHI) ICD2010-4
A multi-stage replica bitline scheme for reducing access time by suppressing enable timing variation of a sense amplifie... [more] ICD2010-4
pp.17-21
ICD 2009-12-15
17:00
Shizuoka Shizuoka University (Hamamatsu) A 3D Processor Using Inductive-Coupling Inter-Chip Link -- 3D System Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM --
Kiichi Niitsu (Keio Univ./JST), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga (Keio Univ.), Itaru Nonomura (Renesas Technology), Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie (Hitachi), Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Tadahiro Kuroda (Keio Univ.) ICD2009-105
A 90nm CMOS processor is mounted face down on a package by C4 bump and a 65nm CMOS 1MB SRAM is glued on it face up. The ... [more] ICD2009-105
pp.163-168
ICD 2008-04-17
10:15
Tokyo   [Invited Talk] 65nm Low-Power High-Density SRAM Operable at 1.0V under 3sigma Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS
Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda, Yasuhisa Shimazaki (Renesas), Kenichi Osada (Hitachi, Ltd.) ICD2008-2
A 1Mb SRAM is fabricated in 65nm LP process with 0.51μm2 cell. An NMOS and PMOS separately applied body bias technique a... [more] ICD2008-2
pp.7-12
ICD 2007-04-12
11:10
Oita   [Invited Talk] A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current
Akira Kotabe, Satoru Hanzawa (Hitachi), Naoki Kitai (Hitachi ULSI), Kenichi Osada, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura (Hitachi), Masahiro Moniwa (Renesas), Takayuki Kawahara (Hitachi) ICD2007-5
An experimental 512-kB embedded Phase Change Memory (PCM) is developed in a 0.13-μm 1.5-V CMOS technology. Three circuit... [more] ICD2007-5
pp.23-28
ICD, ITE-CE 2006-01-26
10:30
Tokyo Kikai-Shinko-Kaikan Bldg. Phase Change RAM Operated with 1.5-V CMOS as Low Cost Embedded Memory
Satoru Hanzawa, Kenichi Osada, Takayuki Kawahara, Riichiro Takemura (Hitachi CRL), Naoki Kitai (Hitachi ULSI), Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi (Hitachi CRL), Hiroshi Moriya (Hitachi MERL), Masahiro Moniwa (Renesas)
This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, u... [more] ICD2005-206
pp.7-12
ICD 2005-04-15
14:00
Fukuoka   Analysys of SRAM neutron-Induced Errors Based on the Consideration of Both Charge-Collection and Parasitic-BipolarFailure Modes
Kenichi Osada (Hitachi), Naoki Kitai (Hitachi ULSI), Shiro Kamohara (Renesas), Takayuki Kawahara (Hitachi)
This paper describes an investigation of the upsetting of values in cells hit by alpha particles or neutrons, in which t... [more] ICD2005-18
pp.31-36
ICD 2004-12-16
10:00
Hiroshima   Dynamic-Vth, Dual-Power-Supply SRAM Cell Using D2G-SOI for Low-Power SoC Application
Masanao Yamaoka, Kenichi Osada, Kiyoo Itoh, Ryuta Tsuchiya, Takayuki Kawahara (Hitachi, Ltd.)
We developped two SRAM memory cells suitable for low-power SoC. The memory cells are composed of new FD-SOI transistors,... [more] ICD2004-183
pp.1-5
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