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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2018-08-07
16:00
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 [Invited Talk] A Battery Management System for Wireless Sensor Devices
Ken-ichi Kawasaki, Jun-ichi Nagata, Hiroyuki Nakamoto (Fujitsu Labs.) SDM2018-34 ICD2018-21
It would be important to observe battery state of charge at each IoT device accurately even with small circuit area and ... [more] SDM2018-34 ICD2018-21
pp.47-52
SDM, ICD 2015-08-25
13:10
Kumamoto Kumamoto City [Invited Talk] 45.5% Energy Reduction by applying DVFS and Multi-Level-Shift Architecture for Low-Power SoCs
Satoshi Tanabe, Atsushi Muramatsu, Ken-ichi Kawasaki, Makoto Mouri, Teruo Ishihara (Flab) SDM2015-69 ICD2015-38
 [more] SDM2015-69 ICD2015-38
pp.63-68
CAS 2012-01-19
16:15
Fukuoka Kyushu Univ. [Invited Talk] Control Techniques of Power Supply Voltage for Low Power LSI
Ken-ichi Kawasaki, Hiroshi Okano, Hisanori Fujisawa, Atsuki Inoue (Fujitsu Lab.) CAS2011-99
It is effective means that power supply voltage is lowered or turned off depending on system usage for suppressing power... [more] CAS2011-99
pp.77-81
CAS 2010-01-28
15:25
Kyoto Kyoudai-Kaikan Bldg. Suppression of Power-supply-voltage Fluctuation on System LSIs using Power Gating technique
Ken-ichi Kawasaki, Koichi Nakayama, Satoshi Tanabe, Hisanori Fujisawa (Fujitsu Lab.) CAS2009-69
A power gating technique minimizing the area overhead of power switches was developed for low power SOCs.
The amount of... [more]
CAS2009-69
pp.31-36
ICD, SDM 2008-07-18
09:50
Tokyo Kikai-Shinko-Kaikan Bldg. A Sub-μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support
Koichi Nakayama, Ken-ichi Kawasaki, Tetsuyoshi Shiota, Atsuki Inoue (Fujitsu Lab.) SDM2008-141 ICD2008-51
A sub-$\micro$s wake-up power gating technique was developed for low power SOCs. It uses two types of power switches and... [more] SDM2008-141 ICD2008-51
pp.77-82
ICD 2005-05-26
10:30
Hyogo Kobe Univ. A Single-Chip Multi-Processor integrating Quadruple Processors on 90nm CMOS Process
Ken-ichi Kawasaki, Tetsuyoshi Shiota, Yukihito Kawabe, Wataru Shibamoto, Atsushi Sato, Tetsutaro Hashimoto, Motoaki Matsumura, Hiroshi Okano, Fumihiko Hayakawa, Shinichiro Tago, Yasuki Nakamura (Fujitsu Labs.), Hideo Miyake (FLT), Atsuhiro Suga, Hiromasa Takahashi, Atsuki Inoue (Fujitsu Labs.)
We have developed a 51.2-GOPS single-chip multi-processor integrating quadruple processors with 1.0-GB/s system-bus dire... [more] ICD2005-21
pp.7-12
 Results 1 - 6 of 6  /   
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