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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 17 of 17  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
COMP 2015-03-09
16:00
Kyoto Ritsumeikan University On a 2-approximation Self-stabilizing Algorithm for the Maximum Leaf Spanning Tree
Keisuke Okamoto, Yoshiaki Katayama (NIT) COMP2014-50
The maximum leaf spanning tree (MLST) is a spanning tree that has the largest possible number of leaves among all spanni... [more] COMP2014-50
pp.53-60
PN 2013-11-11
15:30
Tokyo Waseda University A Study on Long Frame Periods in a Globally-Synchronized Optical Switching Network
Naoya Hara, Keisuke Okamoto, Takahiro Kusuda, Tatsuro Takahashi (Kyoto Univ.) PN2013-27
 [more] PN2013-27
pp.15-20
NS, IN
(Joint)
2013-03-07
11:10
Okinawa Okinawa Zanpamisaki Royal Hotel A Delay-Assurance for Private Line Services in a Grobally-Synchronized Optical Switching Network
Naoya Hara, Keisuke Okamoto, Tatsuro Takahashi (Kyoto Univ.) NS2012-189
In a globally-synchronized optical switching network, delay time occurs in buffers equipped at edge nodes. Some users wa... [more] NS2012-189
pp.141-146
MoNA, AN, USN
(Joint)
2013-01-24
09:00
Miyagi ICHINOBO (Sendai-city) Improving the reliability of vehicle's position announcement by cyclic transmission power control in vehicular networks
Tatsunori Kimpara, Keisuke Okamoto, Susumu Ishihara (Shizuoka Univ) AN2012-44
In the driving safety support systems using direct vehicle-to-vehicle communication, it is important for vehicles to exc... [more] AN2012-44
pp.1-6
PN 2012-11-06
13:05
Tokyo Japan Women's University A study on precision time synchronization in a Grobally-Synchronized Optical Switching Network
Takahiro Kusuda, Keisuke Okamoto, Tatsuro Takahashi (Kyoto Univ.) PN2012-29
 [more] PN2012-29
pp.29-34
PN 2012-11-06
14:40
Tokyo Japan Women's University A Study of Time-slot Assignment Algorithm for Optical Switching Network with Asynchronous Time-Slot Phase
Keisuke Okamoto, Tatsuro Takahashi (Kyoto Univ.) PN2012-31
In this paper, we study time-slot assignment algorithm for sub-lambda switching network which has fine granularity and ... [more] PN2012-31
pp.41-46
PN 2012-03-12
10:55
Nagasaki BaramonNetKan Proposal of a Globally-Synchronized Optical Time-Slot Switching Network
Atsushi Hiramatsu, Masahiro Nakagawa (NTT), Keisuke Okamoto, Shota Takano, Kenji Yokota, Tatsuro Takahashi (Kyoto Univ.) PN2011-83
We propose a cost-effective and power-saving network architecture, globally-synchronized optical time-slot switching net... [more] PN2011-83
pp.7-12
PN 2012-03-12
11:20
Nagasaki BaramonNetKan Examination of Time-Slot Assignment Algorithm in a Grobally-Synchronized Optical Time-Slot Switching Network
Keisuke Okamoto, Shota Takano, Kenji Yokota (Kyoto Univ), Atsushi Hiramatsu, Masahiro Nakagawa (NTT), Tatsuro Takahashi (Kyoto Univ) PN2011-84
This paper focuses on the globally-synchronized optical time-slot switching network and evaluates the time-slot scheduli... [more] PN2011-84
pp.13-18
SDM 2008-03-14
16:15
Tokyo Kikai-Shinko-Kaikan Bldg. New design technology of independent-gate controlled Double-Gate transistor for LSI
Yu Hiroshima, Keisuke Okamoto, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2007-279
 [more] SDM2007-279
pp.33-38
VLD, ICD 2008-03-07
16:10
Okinawa TiRuRu New technology of independent-gate controlled Double-Gate transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-168 ICD2007-191
New design technology of independent-gate controlled Double-Gate transistor realized high density design more than FinFE... [more] VLD2007-168 ICD2007-191
pp.69-74
VLD, ICD 2008-03-07
16:35
Okinawa TiRuRu New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-169 ICD2007-192
New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controll... [more] VLD2007-169 ICD2007-192
pp.75-80
VLD, ICD 2008-03-07
17:00
Okinawa TiRuRu Design of High Density LSI with Three-Dimensional Transistor FinFET -- Effect of pattern Area Reduction with CMOS Cell Library --
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-170 ICD2007-193
(To be available after the conference date) [more] VLD2007-170 ICD2007-193
pp.81-86
ICD, SDM 2007-08-24
13:50
Hokkaido Kitami Institute of Technology Design of High Density LSI with Three-Dimensional Transistor FinFET -- Effect of Pattern Area Reduction with CMOS Cell Library --
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (SIT) SDM2007-163 ICD2007-91
New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of CMO... [more] SDM2007-163 ICD2007-91
pp.119-124
ICD, SDM 2007-08-24
14:15
Hokkaido Kitami Institute of Technology Design Method of system LSI with FinFET type DTMOS
Yu Hiroshima, Shigeyoshi Watanabe, Keisuke Okamoto, Keisuke Koizumi (SIT) SDM2007-164 ICD2007-92
Planar DTMOS has a problem of increase of pattern area. Using FinFET type DTMOS excess pattern area of connect to gate a... [more] SDM2007-164 ICD2007-92
pp.125-130
SDM 2007-03-15
14:20
Tokyo Kikai-Shinko-Kaikan Bldg. Impact of three-dimensional transistor on the pattern area reduction for high density ULSI
Shigeyoshi Watanabe, Keisuke Okamoto, Yuu Hiroshima, Keisuke Koizumi, Makoto Oya (SIT)
 [more] SDM2006-257
pp.15-20
ICD, VLD 2007-03-09
13:40
Okinawa Mielparque Okinawa Design Method of High Density System LSI with Three-Dimensional Transistor (FinFET) -- Pattern Area Reduction of System LSI --
Shigeyoshi Watanabe, Keisuke Okamoto, Makoto Oya (Shonan Institute of Tech.)
 [more] VLD2006-149 ICD2006-240
pp.51-56
ICD, SIP, IE, IPSJ-SLDM 2006-10-27
10:30
Miyagi   Design Method of System LSI with Three-Dimensional Transistor (FinFET) -- Reduction of pattern Area --
Shigeyoshi Watanabe, Keisuke Okamoto, Makoto Oya (SIT)
New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of sys... [more] SIP2006-105 ICD2006-131 IE2006-83
pp.25-30
 Results 1 - 17 of 17  /   
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