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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| COMP | 2019-12-13 10:25 |
Gunma | Ikaho Seminar House, Gunma University | A Note on a Latch/Flip-flop Mixed High-level Synthesis Keisuke Inoue (ICT)  COMP2019-32 |
[more] | COMP2019-32 pp.25-30 |
| CAS, NLP | 2018-10-18 10:00 |
Miyagi | Tohoku Univ. | On the Power-Aware MBU-Tolerant High-Level Synthesis Keisuke Inoue (ICT) CAS2018-37 NLP2018-72 |
[more] | CAS2018-37 NLP2018-72 pp.1-6 |
| CAS, SIP, MSS, VLD | 2018-06-14 09:00 |
Hokkaido | Hokkaido Univ. (Frontier Research in Applied Sciences Build.) | Study on Data Grouping Problem Considering Multiple Bit Upset Tolerance Keisuke Inoue (ICT) CAS2018-1 VLD2018-4 SIP2018-21 MSS2018-1 |
[more] | CAS2018-1 VLD2018-4 SIP2018-21 MSS2018-1 pp.1-6 |
| ISEC, COMP | 2017-12-22 14:15 |
Kochi | Eikokuji Campus, Kochi University of Technology | An ILP Formulation for Maximum Lengh Interval Graph Decomposition Problem Keisuke Inoue (KTC) ISEC2017-88 COMP2017-42 |
[more] | ISEC2017-88 COMP2017-42 pp.107-110 |
| ASN (2nd) |
2017-11-30 10:55 |
Overseas | Eastparc Hotel (Jogjakarta) | The advertisement system for a smart bus stop Hiroki Nishino, Steve Szabo, Keisuke Inoue, Moemi Taniguchi, Mikiko Sode Tanaka (KTC) |
(Advance abstract in Japanese is available) [more] | |
| COMP, IPSJ-AL | 2017-05-13 16:20 |
Nagasaki | Design Conditions and Optimization for RT-level Circuit with Rollback Mechanism Keisuke Inoue (KTC) COMP2017-12 |
[more] | COMP2017-12 pp.85-89 |
|
| MSS, CAS, IPSJ-AL [detail] | 2016-11-25 09:00 |
Hyogo | Kobe Institute of Computing | A Note on Reliablity-Aware Clock Skew Scheduling in High-Level Synthesis Keisuke Inoue (KTC) CAS2016-68 MSS2016-48 |
(To be available after the conference date) [more] | CAS2016-68 MSS2016-48 pp.79-82 |
| IE | 2016-07-01 09:45 |
Okinawa | Study on Compression of Images Including Text by Sparse Coding Keisuke Inoue, Tomo Miyazaki, Yoshihiro Sugaya, Shinichiro Omachi (Tohoku Univ.) IE2016-36 |
For the image and video coding, it is an important task to preserve important information while compressing it into smal... [more] | IE2016-36 pp.5-10 |
|
| VLD, IPSJ-SLDM | 2016-05-11 14:55 |
Fukuoka | Kitakyushu International Conference Center | A Note on Scheduling Problem Considering the Radiation Resistance of Registers Keisuke Inoue (KTC), Mineo Kaneko (JAIST) |
This paper discusses a high-level design of an application specific integrated circuit (ASIC) with radiation resistance.... [more] | |
| VLD | 2016-02-29 16:15 |
Okinawa | Okinawa Seinen Kaikan | A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis Keisuke Inoue (KTC), Mineo Kaneko (JAIST) VLD2015-117 |
This paper discusses a high-level synthesis of new latch-based architecture, HLS-gls. The disadvantage of the conventio... [more] |
VLD2015-117 pp.37-42 |
| PRMU, MVE, CQ, IPSJ-CVIM [detail] | 2012-01-20 16:30 |
Osaka | Various Efforts Towards Performance Improvement of Vision-based MR Tracking Method Using the Feature Landmark Database: Part 2 Keisuke Inoue, Kazuhiro Kitamura, Ryosuke Ichikari, Fumihisa Shibata, Asako Kimura, Hideyuki Tamura (Ritsumeikan Univ.) PRMU2011-183 MVE2011-92 |
We are researching MR-PreViz that assists filmmaking using Mixed Reality, and we adopted the Rehearsal path method (RPM)... [more] | PRMU2011-183 MVE2011-92 pp.365-370 |
|
| VLD | 2011-09-27 11:35 |
Fukushima | University of Aizu | Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis Keisuke Inoue, Mineo Kaneko (JAIST) VLD2011-51 |
[more] | VLD2011-51 pp.61-66 |
| PRMU, MVE, IPSJ-CVIM [detail] | 2011-01-20 14:45 |
Shiga | Various Efforts Towards Performance Improvement of Vision-based MR Tracking Method Using the Feature Landmark Database Kazuhiro Kitamura, Keisuke Inoue, Masato Tsuyumu, Ryosuke Ichikari, Fumihisa Shibata, Hideyuki Tamura (Ritsumeikan Univ.) PRMU2010-172 MVE2010-97 |
We are researching MR-PreViz that assists filmmaking using Mixed Reality. In this research, we adopt "Rehearsal path met... [more] | PRMU2010-172 MVE2010-97 pp.177-182 |
|
| CAS, MSS, VLD, SIP | 2010-06-21 09:00 |
Hokkaido | Kitami Institute of Technology | Clocking Pattern Minimization for Adjustable Safe Clocking-Based Register Assignment Keisuke Inoue (JAIST/JSPS), Mineo Kaneko (JAIST) CAS2010-1 VLD2010-11 SIP2010-22 CST2010-1 |
This work focuses on the timing variation-aware datapath design based on Contra-Data-Direction (CDD) clocking. Although ... [more] | CAS2010-1 VLD2010-11 SIP2010-22 CST2010-1 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 14:05 |
Kochi | Kochi City Culture-Plaza | Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis Keisuke Inoue (JAIST/JSPS), Mineo Kaneko (JAIST) VLD2009-43 DC2009-30 |
In high-level synthesis of LSI, it is an important task to minimize the number of connections between modules (functiona... [more] | VLD2009-43 DC2009-30 pp.13-18 |
| MSS, CAS | 2009-11-27 13:50 |
Aichi | Nagoya University | ILP Formulation of Graph Embedding and Its Application to LSI Routing Keisuke Inoue (JAIST/JSPS), Mineo Kaneko (JAIST) CAS2009-56 CST2009-29 |
This paper proposes an integer linear programming (ILP) formulation of the graph embedding problem, which outputs an opt... [more] | CAS2009-56 CST2009-29 pp.65-70 |
| VLD | 2009-09-24 15:00 |
Osaka | Osaka University | Complete ILP-Formulation of High-Level Synthesis Keisuke Inoue, Mineo Kaneko (JAIST) VLD2009-32 |
In VLSI design, automatic transformation from an algorithm level behavioral description to a RTL (Register Transfer Leve... [more] | VLD2009-32 pp.19-24 |
| SIP, CAS, VLD | 2009-07-01 14:50 |
Hokkaido | Kushiko-shi Shogai Gakushu Center | Resource Sharing and Scheduling Algorithms against Variation of Control Timings Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) CAS2009-5 VLD2009-10 SIP2009-22 |
This paper discusses an overall framework of a RTL datapath which has robustness against the variability of control timi... [more] | CAS2009-5 VLD2009-10 SIP2009-22 pp.25-30 |
| VLD | 2009-03-11 14:00 |
Okinawa | Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) VLD2008-130 |
With the advance of process technology, delay variations have become a serious problem. Recently, the register assignmen... [more] | VLD2008-130 pp.23-28 |
|
| CAS, NLP | 2009-01-23 11:15 |
Miyazaki | A Note on the Number of Extra Registers in Safe Clocking-Based Register Assignment Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) CAS2008-90 NLP2008-120 |
Recently, Backward-Data-Direction (BDD) clocking based register assignment in high-level synthesis has been proposed. BD... [more] | CAS2008-90 NLP2008-120 pp.147-152 |
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