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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2017-04-20
10:35
Tokyo   [Invited Lecture] Sub-3 ns pulse with sub-100 uA switching of 1x-2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS
Daisuke Saida, Saori Kashiwaad, Megumi Yakabe, Tadaomi Daibou, Junichi Ito, Hiroki Noguchi, Keiko Abe, Shinobu Fujita (Toshiba), Miyoshi Fukumoto, Shinji Miwa, Yoshishige Suzuki (Osaka Univ.) ICD2017-2
 [more] ICD2017-2
pp.5-9
SDM 2017-01-30
14:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Level Cache
Yoichi Shiota (AIST), Hiroki Noguchi, Kazutaka Ikegami, Keiko Abe, Shinobu Fujita (Toshiba), Takayuki Nozaki, Shinji Yuasa (AIST), Yoshishige Suzuki (Osaka Univ.) SDM2016-135
In future processing system, the memory capacity of last level cache (LLC) must be increased, because LLC needs to cover... [more] SDM2016-135
pp.21-24
SDM 2016-01-28
15:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme
Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] SDM2015-126
pp.27-30
ICD 2015-04-17
12:40
Nagano   [Invited Talk] Low-power Embedded Perpendicular STT-MRAM Design for Cache Memory
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Chika Tanaka, Chikayoshi Kamata, Minoru Amano, Eiji Kitagawa, Naoharu Shimomura, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) ICD2015-10
 [more] ICD2015-10
pp.45-50
SDM 2015-01-27
14:50
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques
Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2014-142
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, ... [more] SDM2014-142
pp.29-32
SDM 2014-01-29
13:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Variable Nonvolatile Memory Arrays for Adaptive Computing Systems
Hiroki Noguchi, Susumu Takeda, Kumiko Nomura, Keiko Abe, Kazutaka Ikegami, Eiji Kitagawa, Naoharu Shimomura, Junichi Ito, Shinobu Fujita (Toshiba) SDM2013-141
 [more] SDM2013-141
p.29
MRIS, ITE-MMS 2013-07-12
16:35
Tokyo Chuo Univ. Progress on STT MTJ writing Technology and the Effect on Normally-off Computing Systems
Junichi Ito, Hiroaki Yoda, Shinobu Fujita, Naoharu Shimomura, Eiji Kitagawa, Keiko Abe, Kumiko Nomura, Hiroki Noguchi (Toshiba) MR2013-13
We propose a new processor using STT-MRAMs as cache memories. It enables “Normally-off computing”, where the processor i... [more] MR2013-13
pp.37-41
ICD 2013-04-11
15:30
Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Talk] Novel Vertical Magnetization STT-MRAM Technologies for Reducing Power of High Performance Mobile Processors
Shinobu Fujita, Keiko Abe, Hiroki Noguchi, Kumiko Nomura, Eiji Kitagawa, Naoharu Shimomura, Junichi Ito, Hiroaki Yoda (Toshiba) ICD2013-8
 [more] ICD2013-8
pp.39-40
ICD, IPSJ-ARC 2012-01-19
14:20
Tokyo   [Invited Talk] Issues and Prospects of Nonvolatile Memories for Realizing Normally-Off Processors -- How to solve the issues "Dilemma of Nonvolatile Logics --
Shinobu Fujita, Keiko Abe, Kumiko Nomura, Hiroaki Yoda (Toshiba) ICD2011-137
 [more] ICD2011-137
pp.27-31
ICD, IPSJ-ARC 2011-01-21
10:30
Kanagawa Keio University (Hiyoshi Campus) Performance Analysis of 3D-IC for Multi-Core Processors in sub-65m CMOS technologies
Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima (Toshiba)
 [more] ICD2010-134
pp.45-50
ICD 2005-12-16
09:00
Kochi   Ultra Small Random Number Generator for Information Security
Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita (Toshiba Corp.)
We present small random number generators using silicon devices that generate large fluctuating signal as noise source d... [more] ICD2005-192
pp.1-6
 Results 1 - 11 of 11  /   
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