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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-23
10:30		 Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)		 Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool
Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ) VLD2022-56 RECONF2022-79		 Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting att... [more] VLD2022-56 RECONF2022-79
pp.1-6
RECONF 2022-09-07
14:35		 Aichi emCAMPUS STUDIO
(Primary: On-site, Secondary: Online)		 Simulation for a CNN implementation on a multi-FPGA system with system-C description
Shao Ningyu, Hiroaki Suzuki (Keio Univ.), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ.), Hideharu Amano (Keio Univ.) RECONF2022-27		  [more] RECONF2022-27
pp.7-12
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] 2021-01-26
11:20		 Online Online
Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ) VLD2020-60 CPSY2020-43 RECONF2020-79		 (To be available after the conference date) [more] VLD2020-60 CPSY2020-43 RECONF2020-79
pp.119-124
VLD, HWS
(Joint)		 2018-03-01
16:25		 Okinawa Okinawa Seinen Kaikan A Concept of DNN Framework for Embedded System Using FPGA
Ryota Yamamoto, Takuya Okamoto, Shinya Honda (Nagoya Univ.), Qian Zhao, Toki Matsumoto, Yukikazu Nakamoto (Hyogo Univ.), Tamotsu Sakai, Tetsuya Aoyama, Kazutoshi Wakabayashi (NEC) VLD2017-117		 Recently, a DNN (Deep Neural Network) is used in many areas, and it required a field of an embedded system.
For an em... [more]		 VLD2017-117
pp.169-174
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2017-11-07
09:00		 Kumamoto Kumamoto-Kenminkouryukan Parea Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch
Tetsuaki Fujimoto (Ritsumeikan Univ.), Wataru Takahashi, Kazutoshi Wakabayashi (NEC), Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-38 DC2017-44		 This report proposes an optimal implementation of FFT circuit for mixed grained reconfigurable architecture using via-sw... [more] VLD2017-38 DC2017-44
pp.67-72
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-01
17:00		 Nagasaki Nagasaki Kinro Fukushi Kaikan [Fellow Memorial Lecture] Reconfigurable Chips, High-Level Synthesis, and EDA Business
Kazutoshi Wakabayashi (NEC) 		 [more]
DC, CPSY 2015-04-17
13:25		 Tokyo   A study of processor architecture suited for intelligent sensing system
Hiroki Hihara, Akira Iwasaki (Univ. of Tokyo), Masanori Hashimoto (Osaka Univ./JST CREST), Hiroyuki Ochi (Rits/JST CREST), Yukio Mitsuyama (KUT/JST CREST), Hidetoshi Onodera (Kyoto Univ./JST CREST), Hiroyuki Kanbara (ASTEM/JST CREST), Kazutoshi Wakabayashi, Takashi Takenaka, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada (NEC/JST CREST) CPSY2015-8 DC2015-8		 Sensor nodes are now important elements for the system of social infrastructure, and thus intelligent processing capabil... [more] CPSY2015-8 DC2015-8
pp.43-48
RECONF 2013-05-20
17:40		 Kochi Kochi Prefectural Culture Hall Flexible reliability mixed-grained reconfigurable architecture supporting behavioral synthesis
Hiroaki Konoura, Dawood Alnajjar (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. Tech.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Imagawa (Kyoto Univ.), Shinichi Noda, Kazutoshi Wakabayashi (NEC), Masanori Hashimoto, Takao Onoye (Osaka Univ.) RECONF2013-8		 This paper proposes a mixed-grained reconfigurable architecture
that supports C-based behavioral synthesis and flexibl... [more]		 RECONF2013-8
pp.41-46
VLD 2012-03-06
14:00		 Oita B-con Plaza A loop pipeling method for irregular nested loops
Takashi Takenaka, Kazutoshi Wakabayashi (NEC), Yuka Nakagoshi (NIS) VLD2011-126		 This paper presents a behavioral synthesis method for pipelining
irregular nested loops. An irregular nested loop is ... [more]		 VLD2011-126
pp.37-42
 Results 1 - 9 of 9  /   
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