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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 47  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-24
15:25
Kanagawa Raiosha, Hiyoshi Campus, Keio University Measuring SER by Neutron Irradiation Between Volatile SRAM-based and Nonvolatile Flash-based FPGAs
Yuya Kawano, Yuto Tsukita, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2019-90 CPSY2019-88 RECONF2019-80
 [more] VLD2019-90 CPSY2019-88 RECONF2019-80
pp.217-222
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
09:15
Ehime Ehime Prefecture Gender Equality Center NBTI Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement
Takumi Hosaka (Saitama Univ.), Shinichi Nishizawa (Fukuoka Univ.), RYO Kishida (Tokyo Univ. of Science), Takashi Matsumoto (The Univ. of Tokyo), Kazutoshi Kobayashi (Kyoto Institute of Tech.) VLD2019-35 DC2019-59
In this paper, simple and compact Negative Bias Temperature Instability (NBTI) model is proposed. The model is based on ... [more] VLD2019-35 DC2019-59
pp.57-62
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
14:10
Hiroshima Satellite Campus Hiroshima Ultra-long-term Measurement of Aging Degradation on Ring Oscillators by using FPGA and Micro Controller
Hiroki Nakano (KIT), Ryo Kishida (TUS), Jun Furuta, Kazutoshi Kobayashi (KIT) CPM2018-95 ICD2018-56 IE2018-74
 [more] CPM2018-95 ICD2018-56 IE2018-74
pp.31-36
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
13:45
Hiroshima Satellite Campus Hiroshima A Radiation-hard Low-delay Flip-Flop with Stacking Structure for SOI Process
Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2018-69 DC2018-55
 [more] VLD2018-69 DC2018-55
pp.203-208
SDM, ICD, ITE-IST [detail] 2018-08-07
11:30
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 Comparison of Sensitivity to Soft Errors of NMOS and PMOS Transistors by Using Three Types of Stacking Latches in an FDSOI process
Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) SDM2018-28 ICD2018-15
(To be available after the conference date) [more] SDM2018-28 ICD2018-15
pp.15-20
VLD, HWS
(Joint)
2018-02-28
17:20
Okinawa Okinawa Seinen Kaikan Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes
Haruki Maruoka, Kodai Yamada, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-103
The continuous downscaling of transistors has resulted in an increase of reliability issues for semiconductor chips. In ... [more] VLD2017-103
pp.85-90
VLD, HWS
(Joint)
2018-02-28
17:45
Okinawa Okinawa Seinen Kaikan Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage
Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-104
Moore's Law has been miniaturizing integrated circuits, which
can make a lot of high performance devices such as PCs an... [more]
VLD2017-104
pp.91-96
ICD, CPSY, CAS 2017-12-14
15:10
Okinawa Art Hotel Ishigakijima Accelerated Transient Analysis of Power MOSFETs by the Matrix Exponential Method
Tatsuya Kamei, Shigetaka Kumashiro, Kazutoshi Kobayashi (KIT) CAS2017-87 ICD2017-75 CPSY2017-84
In designing and developing power devices, reduction of simulation time is required. In this study, an accurate metric f... [more] CAS2017-87 ICD2017-75 CPSY2017-84
pp.107-112
SDM 2017-11-10
14:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] An Accurate Metric to Control Time Step of Transient Device Simulation by Matrix Exponential Method
Shigetaka Kumashiro, Tatsuya Kamei, Akira Hiroki, Kazutoshi Kobayashi (KIT) SDM2017-70
An accurate metric for the time step control in the power device transient simulation is proposed. This metric contains ... [more] SDM2017-70
pp.47-52
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
14:15
Osaka Ritsumeikan University, Osaka Ibaraki Campus Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations
Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-49 DC2016-43
According to the Moore's law, LSIs are miniaturized and the
reliability of LSIs is degraded. To improve the tolerance ... [more]
VLD2016-49 DC2016-43
pp.31-36
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
14:40
Osaka Ritsumeikan University, Osaka Ibaraki Campus Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System
Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-50 DC2016-44
The impact of soft errors has been serious with process scaling of integrated circuits. Simulation methods for soft erro... [more] VLD2016-50 DC2016-44
pp.37-41
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
15:05
Osaka Ritsumeikan University, Osaka Ibaraki Campus Evaluation of Soft Error Rates of FlipFlops on FDSOI by Heavy Ions
Masashi Hifumi, Shigehiro Umehara, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-51 DC2016-45
We evaluate tolerance for soft errors of FFs on a 28/65 nm FDSOI. We fabricated three different layouts of non-redundant... [more] VLD2016-51 DC2016-45
pp.43-48
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
15:30
Osaka Ritsumeikan University, Osaka Ibaraki Campus Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process
Michitarou Yabuuchi, Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Jun Furuta (KIT), Pieter Weckx (KUL/IMEC), Ben Kaczer (IMEC), Takashi Matsumoto (Univ. of Tokyo), Hidetoshi Onodera (Kyoto Univ.) VLD2016-52 DC2016-46
We propose a circuit analysis method using the bimodal RTN (random telegraph
noise) model of the defect-centric distri... [more]
VLD2016-52 DC2016-46
pp.49-54
ICD, CPSY 2015-12-17
16:00
Kyoto Kyoto Institute of Technology [Poster Presentation] RTN Modeling of Ring Oscillators by a Bimodal Defect-Centric Behavior in a 40 nm process
Azusa Oshima (KIT), Pieter Weckx, Ben Kaczer (IMEC), Takashi Matsumoto (UT), Kazutoshi Kobayashi (KIT), Hidetoshi Onodera (KU)
 [more]
ICD, CPSY 2015-12-18
09:00
Kyoto Kyoto Institute of Technology Evaluation of Soft Error Tolerance of Redundant Flip-Flop in 65nm Bulk and FD-SOI Processes.
Eiji Sonezaki, Kubota Kanto, Masaki Masuda, Shohei Kanda, Jun Furuta, Kazutoshi Kobayashi (KIT) ICD2015-83 CPSY2015-96
According to process down scaling, LSI becomes less reliable for soft errors. To increase the tolerance of FFs for soft ... [more] ICD2015-83 CPSY2015-96
pp.69-74
RECONF 2015-06-19
17:00
Kyoto Kyoto University [Invited Talk] Reliability on Integrated Circuits
Kazutoshi Kobayashi (Kyoto Inst. of Tech.) RECONF2015-13
 [more] RECONF2015-13
p.71
VLD 2015-03-03
09:40
Okinawa Okinawa Seinen Kaikan Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI
Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2014-163
We analyze the efficiency of the design methodology by using circuit
simulations. The design methodology which consider... [more]
VLD2014-163
pp.61-66
ICD, CPSY 2014-12-02
14:50
Tokyo Kikai-Shinko-Kaikan Bldg. Measurements and Evaluations of Aging Degradation Caused by Plasma Induced Damage in 65 nm Process
Ryo Kishida, Azusa Oshima, Kazutoshi Kobayashi (Kyoto Inst. Tech.) ICD2014-106 CPSY2014-118
Degradations of reliability caused by plasma induced damage (PID) have become a significant concern with miniaturizing a... [more] ICD2014-106 CPSY2014-118
pp.123-128
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
11:35
Oita B-ConPlaza Voltage Dependence of Single Event Transient Pulses on 65nm Silicon-on-Thin-BOX and Bulk Processes
Eiji Sonezaki, Kuiyuan Zhang, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2014-84 DC2014-38
Recently, the growth of power consumption has been serious by process
scaling. The lower voltage is most effective to i... [more]
VLD2014-84 DC2014-38
pp.93-97
ICD, SDM 2014-08-04
09:00
Hokkaido Hokkaido Univ., Multimedia Education Bldg. [Invited Talk] A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology
Koichiro Ishibashi (UEC), Nobuyuki Sugii (LEAP), Kimiyoshi Usami (SIT), Hideharu Amano (KU), Kazutoshi Kobayashi (KIT), Cong-Kha Pham (UEC), Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita (LEAP) SDM2014-62 ICD2014-31
 [more] SDM2014-62 ICD2014-31
pp.1-4
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