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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 8 of 8  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2016-06-20
16:15		 Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Internatoinal Conferecen Report: VTS2016
Kazumi Hatayama (Gunma Univ./Creatron Corp.) DC2016-16		 This talk provide a report of VTS2016 (34th IEEE VLSI Test Symposium), which was held in Las Vegas, Nevada, USA, in Apri... [more] DC2016-16
pp.37-42
DC 2013-12-13
13:00		 Ishikawa   Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test
Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue (NAIST) DC2013-68		 This paper presents a scan-based BIST architecture for testing of application-dependent circuits configured on FPGA.
I... [more]		 DC2013-68
pp.1-6
DC 2013-02-13
16:40		 Tokyo Kikai-Shinko-Kaikan Bldg. Data volume reduction method for unknown value handling in built-in self test used in field
Yuta Yoshimi (NAIST), Kazumi Hatayama, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue (NAIST/JST) DC2012-90		 Many approaches on test pattern compression targeted unknown value handling. It is because unknown values have impacts o... [more] DC2012-90
pp.61-66
DC 2012-06-22
16:10		 Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing
Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue (NAIST) DC2012-15		 It is well known that dynamic IR-drop analysis consumes large amount of time even for a few clock cycles. This paper add... [more] DC2012-15
pp.39-44
DC 2011-06-24
14:40		 Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] International Conference Report - VTS2011(29th IEEE VLSI Test Symposium)
Kazumi Hatayama (NAIST) DC2011-11		 This talk provide a report of VTS2011 (29th IEEE VLSI Test Symposium), which was held in Dana Point, California, USA, in... [more] DC2011-11
pp.17-22
DC 2011-02-14
11:25		 Tokyo Kikai-Shinko-Kaikan Bldg. Variation Aware Test Methodology Based on Statistical Static Timing Analysis
Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC) DC2010-62		 The continuing miniaturization of LSI dimension may cause parametric faults which exceed the specification due to proces... [more] DC2010-62
pp.21-26
DC 2009-06-19
14:45		 Tokyo Kikai-Shinko-Kaikan Bldg. Power & Noise Aware Test Utilizing Preliminary Estimation
Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo (STARC) DC2009-15		 Advances in low power design technologies is making issues on power dissipation and IR-drop in testing more serious. Exc... [more] DC2009-15
pp.29-30
DC 2009-02-16
14:40		 Tokyo   Note on Small Delay Fault Model for Intra-Gate Resistive Open Defects
Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki (Tokyo Metro. Univ.), Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC) DC2008-75		  [more] DC2008-75
pp.43-48
 Results 1 - 8 of 8  /   
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