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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
Kanagawa Hiyoshi Campus, Keio University Error detection using residue signed-digit number arithmetic for arithmetic circuits
Yoshitomo Nema, Yuuki Tanaka, Kazuhiro Motegi, Shugang Wei (Gunma Univ) VLD2014-136 CPSY2014-145 RECONF2014-69
For error detection of multiply-accumulate operation, a residue error detector can be considered for the VLSI implementa... [more] VLD2014-136 CPSY2014-145 RECONF2014-69
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
Kanagawa   Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number
Takuya Kobayashi, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2012-114 CPSY2012-63 RECONF2012-68
Signed-Digit (SD) has a redundancy by using \{-1,0,1\}.
By applying the redundant binary representation to arithmetic c... [more]
VLD2012-114 CPSY2012-63 RECONF2012-68
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
Kanagawa Hiyoshi Campus, Keio University Error Checker using Binary tree structure of Residue Signed-Digit Additions
Qian Liu, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2011-111 CPSY2011-74 RECONF2011-70
In this paper, a fast residue checker for error detection of arithmetic circuits is presented. The residue checker consi... [more] VLD2011-111 CPSY2011-74 RECONF2011-70
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
Kanagawa Keio Univ (Hiyoshi Campus) Audio dynamic range compression using polynomial equations
Tatsuya Miyashita, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2010-97 CPSY2010-52 RECONF2010-66
An audio signal level compressor is presented, which is based on the approximation algorithm using an interpolating poly... [more] VLD2010-97 CPSY2010-52 RECONF2010-66
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