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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 36件中 1~20件目  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2018-02-20
09:30
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Weighted Fault Coverage for Two-Pattern Tests
Masayuki Arai (Nihon Univ.), Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2017-77
hrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap... [more] DC2017-77
pp.1-6
DC 2017-12-15
15:05
Akita Akita Study Center, The Open University of Japan Weighted Fault Coverage Considering Via Open Faults
Taiki Kobayashi, Kazuhiko Iwasaki (TMU) DC2017-74
Methods to reduce defect level for VLSI chips have been developed, which is based on weighted fault coverage using criti... [more] DC2017-74
pp.31-36
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-30
09:00
Osaka Ritsumeikan University, Osaka Ibaraki Campus Fast Test Pattern Reordering Based on Weighted Fault Coverage
Shingo Inuyama, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.) VLD2016-61 DC2016-55
Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the ga... [more] VLD2016-61 DC2016-55
pp.99-104
DC 2016-06-20
14:15
Tokyo Kikai-Shinko-Kaikan Bldg. Relationship between the Number of Fan-Outs and Its Wire-length for a logic gate
Taiki Kobayashi, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.) DC2016-12
Many analysis and algorithms have been proposed to reduce wire-lengths based on Steiner trees for VLSI layout designs. A... [more] DC2016-12
pp.13-18
DC 2015-06-16
14:35
Tokyo Kikai-Shinko-Kaikan Bldg. Study on Fast Bridge Fault Test Generation Based on Critical Area
Masayuki Arai (Nihon Univ.), Shingo Inuyama, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2015-17
 [more] DC2015-17
pp.7-12
DC 2014-12-19
15:35
Toyama   Open/Bridge Critical Area Estimation for Weighted Fault Coverage Calculation
Masayuki Arai (Nihon Univ.), Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2014-73
 [more] DC2014-73
pp.33-38
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
09:15
Oita B-ConPlaza Note on Weighted Fault Coverage Considering Multiple Defect Sizes and Via Open
Masayuki Arai (Nihon Univ.), Yuta Nakayama, Kazuhiko Iwasaki (Tokyo Metro. Univ.) VLD2014-97 DC2014-51
 [more] VLD2014-97 DC2014-51
pp.173-178
DC 2014-02-10
11:35
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Weighted Fault Coverage Considering Multiple Defect Sizes and Via Open
Yuta Nakayama (Tokyo Metro. Univ.), Masayuki Arai (Nihon Univ.), Hongbo Shi, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2013-84
 [more] DC2013-84
pp.31-36
DC 2013-10-24
15:00
Tokyo Kikai-Shinko-Kaikan Bldg. A New Machine Learning Based Data Mining Approach for the Network Big Data
Hongbo Shi, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.) DC2013-24
 [more] DC2013-24
pp.19-24
DC 2013-02-13
11:10
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Fault Coverage Estimation Using Critical Area Analysis
Yoshihiro Shimizu, Yuta Nakayama, Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2012-82
 [more] DC2012-82
pp.13-18
DC 2012-06-22
15:20
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg Note on Layout-Aware High Accuracy Estimation of Bridge/Open Fault Coverage
Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2012-13
 [more] DC2012-13
pp.27-32
R 2012-06-15
13:40
Tokyo   Thinning out Checkpoint Sequence in Hybrid State Saving with a Limited Number of Periodical Checkpoints
Ryo Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.) R2012-12
This paper discusses hybrid state saving for applications in which processes should create checkpoints every constant in... [more] R2012-12
pp.7-11
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2012-03-03
14:30
Miyagi   Structure Search of Cascaded TMR for Pipelined Processors Based on Genetic Algorithm
Masayuki Arai, Hajime Ide, Kazuhiko Iwasaki (Tokyo Metro. Univ.) CPSY2011-94 DC2011-98
In this paper we discuss on the application of TMR (Triple Modular Redundancy) to every stage of pipelined processors, a... [more] CPSY2011-94 DC2011-98
pp.211-217
DC 2012-02-13
11:30
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Layout-Aware High Accuracy Estimation of Fault Coverage
Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2011-79
Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the ga... [more] DC2011-79
pp.19-24
DC 2011-12-16
13:00
Hyogo   International Conference Report: PRDC2011 (17th IEEE Pacific Rim International Symposium on Dependable Computing)
Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2011-67
17th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC2011) is going to be held on 12th to 14th, De... [more] DC2011-67
p.1
DC 2011-06-24
13:00
Tokyo Kikai-Shinko-Kaikan Bldg. An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults
Satoshi Fukumoto, Masayuki Arai, Shinya Hara, Kazuhiko Iwasaki (TMU) DC2011-8
In this paper, we analyze the distribution of fault coverage in random-pattern testing. We introduce a stochastic variab... [more] DC2011-8
pp.1-4
DC, CPSY 2011-04-12
16:10
Tokyo   Note on Defect Level Evaluation of Cascaded TMR for Pipeline Processors
Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.) CPSY2011-6 DC2011-6
 [more] CPSY2011-6 DC2011-6
pp.29-34
DC 2011-02-14
16:05
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Area Overhead Reduction for Reconfigurable On-Chip Debug Circui
Masayuki Arai, Yoshihiro Tabata, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2010-69
In this study we evaluate the effectiveness of a reconfigurable on-chip debug circuit, in terms of hardware overhead and... [more] DC2010-69
pp.63-68
DC 2010-06-25
15:45
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Insertion Point and Area of Observation Circuit for On-Chip Debug Technique
Masayuki Arai, Yoshihiro Tabata, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2010-12
 [more] DC2010-12
pp.25-30
DC 2009-12-11
13:25
Shimane   Note on Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test
Anis Uzzaman (Cadence Design Systems/Tokyo Metro. Univ), Brion Keller, Tom Snethen (Cadence), Kazuhiko Iwasaki, Masayuki Arai (Tokyo Metro. Univ) DC2009-57
This paper describes how we provide a mean for dealing with the programmable aspects of on-product clock generation (OPC... [more] DC2009-57
pp.7-12
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