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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 17 of 17  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM, ITE-IST [detail] 2020-08-07
09:30
Online Online [Invited Talk] Understanding the Origin of Low-frequency Noise in Cryo-CMOS Toward Long-coherence-time Si Spin Qubit
Hiroshi Oka, Takashi Matsukawa, Kimihiko Kato, Shota Iizuka, Wataru Mizubayashi, Kazuhiko Endo, Tetsuji Yasuda, Takahiro Mori (AIST) SDM2020-6 ICD2020-6
Si quantum computer has attracted a significant attention due to its potential for large-scale integration using semicon... [more] SDM2020-6 ICD2020-6
pp.25-30
SDM 2019-01-29
09:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Multidomain Dynamics of Ferroelectric Polarization in Negative Capacitance State and its Impacts on Performances of Field-Effect Transistors
Hiroyuki Ota, Tsutomu Ikegami, Koichi Fukuda, Junichi HattoriI, Hidehiro Asai, Kazuhiko Endo, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2018-81
In this paper, we clarified the multidomain dynamics of ferroelectric polarization in the Negative Capacitance Field-Eff... [more] SDM2018-81
pp.1-4
SDM 2018-02-08
10:05
Tokyo Tokyo Univ. [Invited Talk] Cluster-Preforming-Deposited Amorphous WSin (n = 12) Insertion Film of Low SBH and High Diffusion Barrier for Direct Cu Contact
Naoya Okada, Noriyuki Uchida, Shinichi Ogawa, Kazuhiko Endo, Toshihiko Kanayama (AIST) SDM2017-97
 [more] SDM2017-97
pp.1-4
SDM, ICD, ITE-IST [detail] 2017-07-31
12:00
Hokkaido Hokkaido-Univ. Multimedia Education Bldg. TCAD Simulation of C-TFET Circuit with Drain Offset Structure
Hidehiro Asai, Takahiro Mori, Junich Hattori, Koichi Fukuda, Kazuhiko Endo, Takashi Matsukawa (AIST) SDM2017-35 ICD2017-23
We have performed TCAD simulation for a ring oscillator composed of complementary Tunnel Field Effect Transistors (C-TFE... [more] SDM2017-35 ICD2017-23
pp.21-24
SDM 2016-01-28
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Understanding of BTI for Tunnel FETs
Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yuki Ishikawa, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Yongxun Liu, Shinichi O'uchi, Junichi Tsukada, Hiromi Yamauchi, Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo (AIST) SDM2015-122
(To be available after the conference date) [more] SDM2015-122
pp.9-12
SDM, ICD 2015-08-24
15:00
Kumamoto Kumamoto City [Invited Talk] Recent progress and challenges of high-mobility III-V/Ge CMOS technologies for low power LSI applications
Toshifumi Irisawa (AIST), Keiji Ikeda, Yuuichi Kamimuta, Minoru Oda, Tsutomu Tezuka (AIST/Toshiba), Tatsurou Maeda, Hiroyuki Ota, Kazuhiko Endo (AIST) SDM2015-63 ICD2015-32
 [more] SDM2015-63 ICD2015-32
pp.31-36
SDM 2015-01-27
15:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Accurate Prediction of PBTI Lifetime in N-type Fin-Channel High-k Tunnel FETs
Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yongxun Liu, Takashi Matsukawa, Yuki Ishikawa, Kazuhiko Endo, Shinichi Ohuchi, Junichi Tsukada, Hiromi Yamauchi, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2014-143
The positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel FETs (TFETs) with high-k ... [more] SDM2014-143
pp.33-36
SDM 2015-01-27
16:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Scaling Breakthrough for Analog/Digital Circuits by Suppressing Variability and Low-Frequency Noise for FinFETs by Amorphous Metal Gate Technology
Takashi Matsukawa, Koichi Fukuda, Yongxun Liu, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Kazuhiko Endo, Shinichi O'uchi, Shinji Migita, Wataru Mizubayashi, Yukinori Morita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2014-145
 [more] SDM2014-145
pp.41-44
SDM 2015-01-27
16:45
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Experimental Realization of Complementary p- and n- Tunnel FinFETs with Subthreshold Slopes of Less than 60 mV/decade and Very Low (pA/um) Off-Current on a Si CMOS Platform
Yukinori Morita, Takahiro Mori, Koichi Fukuda, Wataru Mizubayashi, Shinji Migita, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2014-146
Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very... [more] SDM2014-146
pp.45-48
ICD 2014-04-18
13:50
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Multigate FinFET Device and Circuit Technology for 10nm and Beyond
Meishoku Masahara, Kazuhiko Endo, Shin-ichi Ouchi, Takashi Matsukawa, Yongxun Liu, Shinji Migita, Wataru Mizubayashi, Yukinori Morita, Hiroyuki Ota (AIST) ICD2014-15
One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a... [more] ICD2014-15
pp.77-82
SDM 2014-01-29
10:50
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Heated Ion Implantation Technology for Highly Reliable Metal-gate/High-k CMOS SOI FinFETs
Wataru Mizubayashi (AIST), Hiroshi Onoda, Yoshiki Nakashima (Nissin Ion Equipment), Yuki Ishikawa, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Shinichi Ouchi, Junichi Tsukada, Hiromi Yamauchi, Shinji Migita, Yukinori Morita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2013-138
The impact of heated ion implantation (I/I) technology on metal-gate (MG)/high-k (HK) CMOS SOI FinFET performance and re... [more] SDM2013-138
pp.13-16
SDM, ICD 2013-08-01
09:25
Ishikawa Kanazawa University Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect
Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Kazuhiko Endo, Takashi Matsukawa, Shin-ichi O'uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2013-66 ICD2013-48
A synthetic electric field effect to enhance the performance of tunnel field-effect transistors (TFETs) is proposed. The... [more] SDM2013-66 ICD2013-48
pp.7-12
ICD, ITE-IST 2013-07-05
16:50
Hokkaido San Refre Hakodate A Study on 1/f Noise Characteristic in Independent-Double-Gate-FinFET
Hideo Sakai (Keio Univ.), Shin-ichi O'uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Yuki Ishikawa, Junichi Tsukada, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Meishoku Masahara (AIST), Hiroki Ishikuro (Keio Univ.) ICD2013-43
In this work, we measured 1/f noise of Independent-Double-Gate- (IDG-) FinFET which has two independent gates. Flicker n... [more] ICD2013-43
pp.119-124
SDM, ED
(Workshop)
2012-06-29
10:45
Okinawa Okinawa Seinen-kaikan [Invited Talk] Decomposition analysis of on-current variability of FinFETs
Takashi Matsukawa, Yongxun Liu, Kazuhiko Endo, Shinichi O'uchi, Meishoku Masahara (AIST)
 [more]
ICD 2011-04-19
10:55
Hyogo Kobe University Takigawa Memorial Hall 0.5-V FinFET SRAM Using Dynamic-Threshold-Voltage Pass Gates
Shin-ichi O'uchi, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara (AIST) ICD2011-11
This article presents a FinFET SRAM which salvages malfunctioned bits caused by random variation. In the presenting SRAM... [more] ICD2011-11
pp.59-63
SDM, ED 2011-02-23
16:30
Hokkaido Hokkaido Univ. A Study on Precise FinFET High Frequency Characteristic Evaluation Method
Hideo Sakai (Keio Univ.), Shinichi Ouchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara (AIST), Hiroki Ishikuro (Keio Univ.) ED2010-198 SDM2010-233
In recent years, different research groups have been focusing on FinFET transistor research as an excellent replacement ... [more] ED2010-198 SDM2010-233
pp.37-42
ICD, SDM 2010-08-27
16:25
Hokkaido Sapporo Center for Gender Equality On the Gate-Stack Origin Threshold Voltage Variability in Scaled FinFETs and Multi-FinFETs
Yongxun Liu, Kazuhiko Endo, Shinich Ouchi (AIST), Takahiro Kamei (Meiji Univ.), Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa (AIST), Tetsuro Hayashida (Meiji Univ.), Kunihiro Sakamoto, Takashi Matsukawa (AIST), Atsushi Ogura (Meiji Univ.), Meishoku Masahara (AIST) SDM2010-151 ICD2010-66
The threshold voltage (Vt) variability in scaled FinFETs with gate length down to 20 nm was systematically investigated.... [more] SDM2010-151 ICD2010-66
pp.149-154
 Results 1 - 17 of 17  /   
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