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Committee Date Time Place Paper Title / Authors Abstract Paper #
SCE 2007-10-17
14:15
Tokyo Kikai-Shinko-Kaikan Bldg. Optimization in ramp fabrication process for high-Tc ramp-edge Josephson junction
Seiji Adachi, Kaku Igarashi, Kiyokazu Higuchi, Hironori Wakana (SRL), Nobuyuki Iwata, Hiroshi Yamamoto (Nihon Univ.), Keiichi Tanabe (SRL)
For fabrication of integrated circuits including high-Tc ramp-edge Josephson junctions, the establishment of preparation... [more] SCE2007-21
pp.17-21
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