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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, IPSJ-ARC 2008-05-13
10:30		 Tokyo   An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping
Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.) 		In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which e... [more] ICD2008-20
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