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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 20件中 1~20件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, CPSY 2014-12-01
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. [Poster Presentation] A Study on a Comprehensive Architecture Exploration Environment for Emerging Applications
Shohei Takeuchi, Shinya Takamaeda Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST)
Emerging applications, such as graph processing and machine learning, contain several irregular memory access patterns a... [more] ICD2014-77 CPSY2014-89
pp.25-27
ICD, CPSY 2014-12-01
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. [Poster Presentation] A Study on Intelligent Memory System for Overcomming Data Moving Bottlenecks
Tadahiro Edamoto, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (naist)
 [more] ICD2014-79 CPSY2014-91
pp.31-33
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
15:10
Oita B-ConPlaza A Large Graph Segmentation Method for Triangle Counting
Tatsuhiro Hirano, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (NAIST)
We previously proposed a breadth-first-search (BFS) triangle counting method to fast get the triangle counts of a graph.... [more] CPSY2014-73
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
15:35
Oita B-ConPlaza Parallelization of Shortest Path Search on Various Platforms and Its Evaluation
Shuto Kurebayashi, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (NAIST)
Since graph processing has irregular control flows and memory access patterns, its acceleration by the parallelization i... [more] CPSY2014-74
pp.13-18
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
10:05
Oita B-ConPlaza Implementation and Evaluation of An Accelerator based on Manymemory Network
Ryo Shimizu, Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST)
In this research, we focus on the data parallelization of stencil computations on a previously proposed memory-network b... [more] CPSY2014-81
pp.51-56
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
10:30
Oita B-ConPlaza Convolutional Neural Network Processing on An Accelerator based on Manymemory Network
Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST)
Recently, Convolutional Neural Network (CNN) is widely used for image recognition. GPU is generally preferred to acceler... [more] CPSY2014-82
pp.57-62
CPSY, DC
(Joint)
2014-07-28
13:15
Niigata Toki Messe, Niigata An FPGA-based Graph Processing Accelerator with PyCoRAM
Shinya Takamaeda-Yamazaki, Tadahiro Edamoto, Jun Yao, Yasuhiko Nakashima (NAIST)
In order to improve the programmablity of FPGA-based accelerators with higher performance, we are developing PyCoRAM tha... [more] CPSY2014-10
pp.1-6
CPSY, DC
(Joint)
2014-07-28
13:40
Niigata Toki Messe, Niigata High Performance Graph Processing with a Memory Intensive Array Accelerator
Ryo Shimizu, Shinya Takamaeda Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST)
A speedup technique incorporating a CGRA equipped with a local memory attached to each execution unit for accelerating t... [more] CPSY2014-11
pp.7-12
CPSY, DC
(Joint)
2014-07-30
09:25
Niigata Toki Messe, Niigata Instruction Execution Method towards Error Reduction of Neural Network Processing
Kazuma Koike, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST)
Approximate Computing has attracted attention as a method for reducing power consumption in varies applications, such as... [more] CPSY2014-33
pp.137-142
VLD 2013-03-06
15:35
Okinawa Okinawa Seinen Kaikan Robust Redundant Circuit Structure to Mitigate Wearout by Reversing Register Values
Shogo Okada, Masaki Masuda (Kyoto Inst. of Tech.), Jun Yao, Hajime Shimada (NAIST), Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
 [more] VLD2012-162
pp.147-152
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
09:10
Kanagawa   An accelerator with minimal data transferring using ring connections
He Guan, Jun Yao, Yasuhiko Nakashima (NAIST)
(To be available after the conference date) [more] VLD2012-123 CPSY2012-72 RECONF2012-77
pp.93-98
DC, CPSY
(Joint)
2012-08-02
15:45
Tottori Torigin Bunka Kaikan *
Ryosuke Yamanaka, Jun Yao, Yasuhiko Nakashima (NAIST)
 [more] CPSY2012-13
pp.25-30
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-28
13:25
Miyazaki NewWelCity Miyazaki Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops
Shogo Okada, Masaki Masuda (KIT), Jun Yao, Hajime Shimada (NAIST), Kazutoshi Kobayashi (KIT)
Soft-error rates are becoming larger due to process scaling. Various ways of prediction for soft-error
are being tried.... [more]
VLD2011-59 DC2011-35
pp.43-48
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-29
13:25
Miyazaki NewWelCity Miyazaki A Scaling Method for a Large FU Array Accerlator on Multiple FPGAs
Kodai Moritaka, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST)
We proposed previously Linear Array Pipeline Processor (LAPP), which can be used to map an inner
loop of conventional V... [more]
CPSY2011-44
pp.9-14
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-29
14:40
Miyazaki NewWelCity Miyazaki Implementation of an FU Array Accelerator and its Analysis
Mitsutoshi Saito, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST)
We have previously proposed Linear Array Pipeline Processor (LAPP), which can map an inner loop of conventional VLIW cod... [more] CPM2011-159 ICD2011-91
pp.53-58
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-30
10:05
Miyazaki NewWelCity Miyazaki A DMR based Parmanent Error Locating Method for a Dependable FU Array
Yohei Hazama, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST)
Triple Modular Redundancy (TMR) is widely used to locating the erroneous unit inside electronic device when the possibil... [more] CPSY2011-51
pp.47-52
DC, CPSY
(Joint)
2011-07-28
15:15
Kagoshima   Proposal for High Efficient DVS Using Adaptive Redundancy of FUs
Yukihiro Sasagawa, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST)
Recently, the well-known low power technology DVS(Dynamic Voltage Scaling) is aggressively applied to processors with Ra... [more] DC2011-15
pp.1-6
EMD 2007-11-15
15:00
Shizuoka Actcity Hamamatsu An Improved Method to Measure Current Density Distribution in the Root of a Moving Arc at the Cathode Surface
Tiejun Xu, Mingzhe Rong, Yi Wu, Xiaohua Wang, Qiang Ma, Jianjun Yao (Xi'an Jiaotong Univ.)
The results of current distribution obtained by M. G. Drouet and his cooperators was only line integral value of the cur... [more] EMD2007-96
pp.161-164
ICD, IPSJ-ARC 2007-06-01
14:15
Kanagawa   The Dynamic Instruction Scheduler for ALU Cascading
Kosuke Ogata, Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita (Kyoto Univ.)
 [more] ICD2007-32
pp.91-96
ICD, IPSJ-ARC 2006-06-08
11:30
Kanagawa   Dynamic Control Mechanisms for Pipeline Stage Unification Based on Program Phase Detection
Jun Yao, Hajime Shimada (Kyoto Univ.), Yasuhiko Nakashima (NAIST), Shin-ichiro Mori (Fukui Univ.), Shinji Tomita (Kyoto Univ.)
To reduce the power consumption in mobile processors, a method called Pipeline Stage Unification (PSU) is previously des... [more] ICD2006-43
pp.19-24
 20件中 1~20件目  /   
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