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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 8件中 1~8件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2016-06-20
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. A Binding Method for Testability to Generate Easily Testable Functional Time Expansion Models
Mamoru Sato, Toshinori hosokawa, Tetsuya Masuda, Jun Nishimaki (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2016-14
A test generation method for datapaths using easily testable functional time expansion models was proposed as efficient ... [more] DC2016-14
pp.25-30
DC 2015-02-13
11:55
Tokyo Kikai-Shinko-Kaikan Bldg Test Method for Encryption LSI against Scan-based Attacks
Masayoshi Yoshimura (Kyoto Sangyo Univ.), Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.) DC2014-82
 [more] DC2014-82
pp.25-30
DC 2015-02-13
14:55
Tokyo Kikai-Shinko-Kaikan Bldg A Method of Scheduling in High-Level Synthesis for Hierarchical Testability
Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-84
We previously proposed a binding method for hierarchical testability to increase the number of hierarchically testable f... [more] DC2014-84
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
10:30
Oita B-ConPlaza A Multi Cycle Capture Test Generation Method to Reduce Capture Power Dissipation
Hiroshi Yamazaki, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) VLD2014-100 DC2014-54
 [more] VLD2014-100 DC2014-54
pp.191-196
DC 2014-06-20
16:00
Tokyo Kikai-Shinko-Kaikan Bldg. A Binding Method for Hierarchical Testability Using Results of Test Environment Generation
Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-16
Hierarchical test generation methods using functional register-transfer level circuits have been proposed as efficient t... [more] DC2014-16
pp.39-44
DC 2014-06-20
16:25
Tokyo Kikai-Shinko-Kaikan Bldg. An evaluation for Testability of Functional k-Time Expansion Models
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-17
A test generation method using functional k-time expansion models for data paths was proposed. In the test generation
m... [more]
DC2014-17
pp.45-50
DC 2014-02-10
16:00
Tokyo Kikai-Shinko-Kaikan Bldg. A Low Power Consumption Oriented Test Generation Method for Transition Faults Using Multi Cycle Capture Test Generation
Hiroshi Yamazaki, Yuto Kawatsure, Jun Nishimaki, Atsushi Hirai, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Koji Yamazaki (Meiji Univ) DC2013-89
High power dissipation can occur when the response to a test pattern is captured by flip-flops in at-speed scan testing,... [more] DC2013-89
pp.61-66
DC 2013-06-21
13:45
Tokyo Kikai-Shinko-Kaikan Bldg. A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits
Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10
In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design pro... [more] DC2013-10
pp.1-6
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