IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 19件中 1~19件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-24
15:25
Kanagawa Raiosha, Hiyoshi Campus, Keio University Measuring SER by Neutron Irradiation Between Volatile SRAM-based and Nonvolatile Flash-based FPGAs
Yuya Kawano, Yuto Tsukita, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2019-90 CPSY2019-88 RECONF2019-80
 [more] VLD2019-90 CPSY2019-88 RECONF2019-80
pp.217-222
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
14:10
Hiroshima Satellite Campus Hiroshima Ultra-long-term Measurement of Aging Degradation on Ring Oscillators by using FPGA and Micro Controller
Hiroki Nakano (KIT), Ryo Kishida (TUS), Jun Furuta, Kazutoshi Kobayashi (KIT) CPM2018-95 ICD2018-56 IE2018-74
 [more] CPM2018-95 ICD2018-56 IE2018-74
pp.31-36
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
13:45
Hiroshima Satellite Campus Hiroshima A Radiation-hard Low-delay Flip-Flop with Stacking Structure for SOI Process
Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2018-69 DC2018-55
 [more] VLD2018-69 DC2018-55
pp.203-208
SDM, ICD, ITE-IST [detail] 2018-08-07
11:30
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 Comparison of Sensitivity to Soft Errors of NMOS and PMOS Transistors by Using Three Types of Stacking Latches in an FDSOI process
Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) SDM2018-28 ICD2018-15
(To be available after the conference date) [more] SDM2018-28 ICD2018-15
pp.15-20
VLD, HWS
(Joint)
2018-02-28
17:20
Okinawa Okinawa Seinen Kaikan Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes
Haruki Maruoka, Kodai Yamada, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-103
The continuous downscaling of transistors has resulted in an increase of reliability issues for semiconductor chips. In ... [more] VLD2017-103
pp.85-90
VLD, HWS
(Joint)
2018-02-28
17:45
Okinawa Okinawa Seinen Kaikan Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage
Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-104
Moore's Law has been miniaturizing integrated circuits, which
can make a lot of high performance devices such as PCs an... [more]
VLD2017-104
pp.91-96
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
14:15
Osaka Ritsumeikan University, Osaka Ibaraki Campus Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations
Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-49 DC2016-43
According to the Moore's law, LSIs are miniaturized and the
reliability of LSIs is degraded. To improve the tolerance ... [more]
VLD2016-49 DC2016-43
pp.31-36
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
14:40
Osaka Ritsumeikan University, Osaka Ibaraki Campus Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System
Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-50 DC2016-44
The impact of soft errors has been serious with process scaling of integrated circuits. Simulation methods for soft erro... [more] VLD2016-50 DC2016-44
pp.37-41
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
15:05
Osaka Ritsumeikan University, Osaka Ibaraki Campus Evaluation of Soft Error Rates of FlipFlops on FDSOI by Heavy Ions
Masashi Hifumi, Shigehiro Umehara, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-51 DC2016-45
We evaluate tolerance for soft errors of FFs on a 28/65 nm FDSOI. We fabricated three different layouts of non-redundant... [more] VLD2016-51 DC2016-45
pp.43-48
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
15:30
Osaka Ritsumeikan University, Osaka Ibaraki Campus Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process
Michitarou Yabuuchi, Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Jun Furuta (KIT), Pieter Weckx (KUL/IMEC), Ben Kaczer (IMEC), Takashi Matsumoto (Univ. of Tokyo), Hidetoshi Onodera (Kyoto Univ.) VLD2016-52 DC2016-46
We propose a circuit analysis method using the bimodal RTN (random telegraph
noise) model of the defect-centric distri... [more]
VLD2016-52 DC2016-46
pp.49-54
ICD, CPSY 2015-12-18
09:00
Kyoto Kyoto Institute of Technology Evaluation of Soft Error Tolerance of Redundant Flip-Flop in 65nm Bulk and FD-SOI Processes.
Eiji Sonezaki, Kubota Kanto, Masaki Masuda, Shohei Kanda, Jun Furuta, Kazutoshi Kobayashi (KIT) ICD2015-83 CPSY2015-96
According to process down scaling, LSI becomes less reliable for soft errors. To increase the tolerance of FFs for soft ... [more] ICD2015-83 CPSY2015-96
pp.69-74
ICD, CPSY 2015-12-18
12:40
Kyoto Kyoto Institute of Technology [Invited Talk] Evaluation of Radiation-induced Soft Errors on LSI
Jun Furuta (KIT) ICD2015-87 CPSY2015-100
 [more] ICD2015-87 CPSY2015-100
pp.87-92
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
11:35
Oita B-ConPlaza Voltage Dependence of Single Event Transient Pulses on 65nm Silicon-on-Thin-BOX and Bulk Processes
Eiji Sonezaki, Kuiyuan Zhang, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2014-84 DC2014-38
Recently, the growth of power consumption has been serious by process
scaling. The lower voltage is most effective to i... [more]
VLD2014-84 DC2014-38
pp.93-97
VLD 2014-03-05
10:25
Okinawa Okinawa Seinen Kaikan Evaluation of Multiple Cell Upsets Considering Parasitic Bipolar Effects
Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) VLD2013-157
As a result of the process scaling, radiation-induced Multiple Cell
Upsets (MCUs) become major issue for LSI reliabilit... [more]
VLD2013-157
pp.125-130
ICD 2012-12-18
11:45
Tokyo Tokyo Tech Front A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop
Masaki Masuda, Kanto Kubota, Ryosuke Yamamoto (KIT), Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (KIT), Hidetoshi Onodera (Kyoto Univ.) ICD2012-117
We propose a low-power redundant flip-flop to be operated with high reliability over 1 GHz clock frequency based on the ... [more] ICD2012-117
pp.109-113
ICD 2011-12-16
09:55
Osaka   A 65-nm Radiation-Hard Flip-Flop Tolerant to Multiple Cell Upsets
Ryosuke Yamamoto, Chikara Hamanaka (Kyoto Inst. of Tech.), Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) ICD2011-129
MCUs in redundant FFs is a dominant factor in a current deep-submicron process. A layout structure to avoid MCUs is prop... [more] ICD2011-129
pp.131-136
ICD, SDM 2010-08-27
14:10
Hokkaido Sapporo Center for Gender Equality A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element
Jun Furuta (Kyoto Univ.), Chikara Hamanaka, Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) SDM2010-146 ICD2010-61
 [more] SDM2010-146 ICD2010-61
pp.121-124
VLD 2010-03-10
15:25
Okinawa   Generation Mechanism of SEU and MCU Caused by Parasitic Lateral Bipolar Transitstors
Chikara Hamanaka (Kyoto Institute of Tech.), Jun Furuta, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Institute of Tech.), Hidetoshi Onodera (Kyoto Univ./JST, CREST) VLD2009-103
Tolerance for soft-error decreases as integration advances. SEU(Single Event Upset), flipping one bit
and MCU(Multi-Cel... [more]
VLD2009-103
pp.25-30
EE 2005-02-09
14:50
Fukuoka   Characteristic Analysis of Multiple-Input Buck-Boost Converter in Discontinuous Current Mode
Jun Furuta, Fujio Kurokawa, Hirofumi Matsuo (Nagasaki Univ.)
In the power-supply unit using the clean energy such as the solar array,wind generator and fuel cell,it is important not... [more] EE2004-76
pp.63-68
 19件中 1~19件目  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : 以上の論文すべての著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan