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Committee Date Time Place Paper Title / Authors Abstract Paper #
ED, SDM 2010-07-02
12:05		 Tokyo Tokyo Inst. of Tech. Ookayama Campus A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process
Jae-Young Park, Dae-Woo Kim, Young-San Son, Jong-Chan Ha, Jong-Kyu Song, Chang-Soo Jang, Won-Young Jung (Dongbu HiTek) ED2010-111 SDM2010-112		  [more] ED2010-111 SDM2010-112
pp.269-274
SDM, ED 2009-06-24
16:00		 Overseas Haeundae Grand Hotel, Busan, Korea Analysis on the Behavior of a Low Voltage Triggered SCR ESD Clamp Circuit in Comparison between the Standard Transmission Line Pulse System and the Very Fast Transmission Line Pulse System.
Jae-Young Park, Jong-Kyu Song, Dae-Woo Kim, Chang-Soo Jang, Won-Young Jung, Taek-Soo Kim (Dongbu HiTek) ED2009-54 SDM2009-49		  [more] ED2009-54 SDM2009-49
pp.17-20
SDM, ED 2008-07-11
11:35		 Hokkaido Kaderu２・７ A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology
Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, Joon-Tae Jang, San-Hong Kim, Sung-Ki Kim, Taek-Soo Kim (Dongbu HiTek) ED2008-76 SDM2008-95		 The holding voltage of the high-voltage devices the snapback breakdown condition has been known to be much smaller than ... [more] ED2008-76 SDM2008-95
pp.193-197
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