IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 25件中 1~20件目  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD 2019-02-27
11:15
Okinawa Okinawa Ken Seinen Kaikan A Case Study on Approximate Multipliers for MNIST CNN
Kenta Shirane, Takahiro Yamamoto (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-95 HWS2018-58
 [more] VLD2018-95 HWS2018-58
pp.13-18
HWS, VLD 2019-02-27
14:30
Okinawa Okinawa Ken Seinen Kaikan Function-level Module Sharing with High-level Synthesis
Ryohei Nozaki (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-100 HWS2018-63
High-Level Synthesis (HLS) which automatically synthesizes a Resister-Transfer Level (RTL) circuit from a behavioral des... [more] VLD2018-100 HWS2018-63
pp.43-48
HWS, VLD 2019-02-27
14:55
Okinawa Okinawa Ken Seinen Kaikan High-Level Synthesis of the CHStone Benchmark Programs with SDSoC
Takuya Adachi (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-101 HWS2018-64
In recent years, High-Level Synthesis (HLS), which automatically generates hardware circuits from software program, have... [more] VLD2018-101 HWS2018-64
pp.49-54
HWS, VLD 2019-02-27
16:20
Okinawa Okinawa Ken Seinen Kaikan A Battery Degradation aware System Level Battery Management Methodology
Daichi Watari, Ittetsu Taniguchi, Takao Onoye (Osaka Univ.) VLD2018-104 HWS2018-67
The battery degradation is a serious problem for the modern electrical systems. This paper proposes State of Health (SOH... [more] VLD2018-104 HWS2018-67
pp.67-72
HWS, VLD 2019-02-27
16:45
Okinawa Okinawa Ken Seinen Kaikan Design of an FPGA-based Manycore Architecture with Selective Local/Global Memory
Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-105 HWS2018-68
FPGA-based manycore architectures attract an increasing attention in order to realize high-performance embedded systems.... [more] VLD2018-105 HWS2018-68
pp.73-78
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-05
09:55
Hiroshima Satellite Campus Hiroshima A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones
Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-41 DC2018-27
 [more] VLD2018-41 DC2018-27
pp.7-11
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
10:30
Hiroshima Satellite Campus Hiroshima A Case Study on Memory Architecture Exploration for FPGA-based Manycores
Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-53 DC2018-39
In the design of high-performance embedded systems, FPGA-based manycores attract an increasing attention. In embedded sy... [more] VLD2018-53 DC2018-39
pp.101-106
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
15:55
Hiroshima Satellite Campus Hiroshima Malleable Task Scheduling for Energy Minimization on Heterogeneous Multicores
Hiroki Nishikawa, Kana Shimada (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-63 DC2018-49
 [more] VLD2018-63 DC2018-49
pp.171-176
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
16:20
Hiroshima Satellite Campus Hiroshima Communication-Aware Scheduling for Data-Parallel Tasks
Kana Shimada (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-64 DC2018-50
 [more] VLD2018-64 DC2018-50
pp.177-182
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
10:55
Osaka Ritsumeikan University, Osaka Ibaraki Campus Scheduling of Malleable Fork-Join Tasks
Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2016-45 DC2016-39
This paper studies scheduling of malleable fork-join tasks. In our scheduling problem, each task can be partitioned into... [more] VLD2016-45 DC2016-39
pp.7-11
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-29
17:20
Kanagawa Hiyoshi Campus, Keio University A Dual-mode Scheduling Strategy for Task Graphs with Data Parallelism
Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2014-128 CPSY2014-137 RECONF2014-61
 [more] VLD2014-128 CPSY2014-137 RECONF2014-61
pp.105-109
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-27
10:50
Kagoshima   A Hardware/Software Simulator for NoC using SystemC and QEMU
Yosuke Kurimoto, Yusuke Fukutsuka, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-69 DC2013-35
 [more] VLD2013-69 DC2013-35
pp.63-68
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-28
09:20
Kagoshima   Function-Level Profiling for Embedded Software with QEMU
Tran Van Dung, Ittetsu Taniguchi (Ritsumeikan Univ.), Takuji Hieda (Kyushu Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-78 DC2013-44
Function-level profiling is crucial for optimized embedded software which needs to have resource constraint, low level p... [more] VLD2013-78 DC2013-44
pp.125-128
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-28
11:20
Kagoshima   List Scheduling Algorithms for Task Graphs with Data Parallelism
Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama, Lin Meng (Ritsumeikan Univ.) VLD2013-90 DC2013-56
 [more] VLD2013-90 DC2013-56
pp.215-220
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
11:15
Kagoshima   Estimation for Method of Controller Implementation in High-Level Synthesis
Ryoya Sobue (Ritsumeikan Univ.), Yuko Hara-Azumi (NAIST), Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-96 DC2013-62
 [more] VLD2013-96 DC2013-62
pp.257-262
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
11:20
Fukuoka Centennial Hall Kyushu University School of Medicine Controller Synthesis for Clock Improvement in Behavioral Synthesis
Ryoya Sobue (Ritsumeikan Univ.), Yuko Hara-Azumi (NAIST), Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2012-78 DC2012-44
 [more] VLD2012-78 DC2012-44
pp.111-116
VLD 2011-03-02
13:10
Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center An Architecture Exploration Method based on a Branch-and-Bound Strategy for Embedded VLIW Processors
Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) VLD2010-116
This paper proposes an architecture exploration method based on a branch-and-bound strategy for embedded VLIW processors... [more] VLD2010-116
pp.1-6
VLD 2011-03-02
13:35
Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Energy-Aware Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors with Multi-Cycle Instructions
Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) VLD2010-117
Reducing energy consumption is a crucial for the embedded system design, and especially, the leakage energy reduction is... [more] VLD2010-117
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-30
09:50
Fukuoka Kyushu University Energy Aware Instruction Scheduling for Fine Grained Power Gated VLIW Processors
Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) VLD2010-65 DC2010-32
Reducing energy consumption is a crucial for the embedded system design, and especially, the leakage energy reduction is... [more] VLD2010-65 DC2010-32
pp.61-66
VLD 2009-09-25
10:00
Osaka Osaka University An Approach for Algorithm Tuning of Power Grid Simulation by GPGPU
Makoto Yokota, Yuuya Isoda, Hisako Sugano, Ittetsu Taniguchi, Masahiro Fukui (Ritsumeikan Univ.) VLD2009-36
This paper proposes a speeding up technique for massively parallel power gird simulator by GPGPU (General Purpose comput... [more] VLD2009-36
pp.39-44
 25件中 1~20件目  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan