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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2014-04-18
13:00		 Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] A 28nm 400MHz 4-Parallel 1.6Gsearch/s 80Mb Ternary CAM
Koji Nii, Teruhiko Amano, Naoya Watanabe (Renesas Electronics), Minoru Yamawaki, Kenji Yoshinaga, Mihoko Wada (Renesas System Desgin), Isamu Hayashi (Renesas Electronics) ICD2014-14		  [more] ICD2014-14
pp.71-76
ICD 2013-04-12
15:55		 Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Lecture] A 250MHz 18Mb Full Ternary CAM with 0.3V Match Line Sense Amplifier in 65nm CMOS
Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, Masaya Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai (Renesas Electronics) ICD2013-22		 An 18Mb full ternary CAM with 0.3V match line sense amplifier (LV-MA) is designed and fabricated in 65nm bulk CMOS proce... [more] ICD2013-22
pp.115-120
ICD, SDM 2012-08-03
15:30		 Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido A Low Voltage High-Speed Inductive-Coupling Transceiver with Adaptive Pulse Width Controller Using Multi-Phase Oscillator
Yuki Urano, Takeshi Matsubara (Keio Univ.), Isamu Hayashi (STARC), Abul Hasan Johari, Kaoru Kohira, Teruo Jyo, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ.) SDM2012-86 ICD2012-54		 This paper presents a pulse-based inductive-coupling transceiver with adaptive pulse width controller for high-speed wir... [more] SDM2012-86 ICD2012-54
pp.127-132
ICD, ITE-IST 2011-07-22
16:10		 Hiroshima Hiroshima Institute of Technology An 0.5V Transceiver in 65nm CMOS for High-Speed Wireless Proximity Interface
Takeshi Matsubara (Keio Univ.), Isamu Hayashi (STARC), Abul Hasan Johari, Satoshi Kumaki, Kaoru Kohira, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ.) ICD2011-36		 This paper presents a pulse-based inductive-coupling transceiver in 65nm CMOS for High-speed wireless proximity communic... [more] ICD2011-36
pp.119-123
ICD 2010-12-16
15:10		 Tokyo RCAST, Univ. of Tokyo [Poster Presentation] A 0.5V 6-bit Scalable Phase Interpolator
Satoshi Kumaki, Abul Hasan Johari, Takeshi Matsubara (Keio Univ), Isamu Hayashi (STARC), Hiroki Ishikuro (Keio Univ) ICD2010-110		 This paper proposes a scalable phase interpolator (PI) with dual-input inverter. A pipelined architecture is proposed to... [more] ICD2010-110
p.81
ICD 2007-04-13
11:00		 Oita   [Invited Talk] A high density embedded memory for Soc: Twin transistor RAM(TT-RAM)
Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka (Renesas) ICD2007-13		 A high speed/low power dissipation high density Twin transistor RAM(TT-RAM) has been developed as SOI CMOS platform memo... [more] ICD2007-13
pp.71-76
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