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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2018-04-19
14:55		 Tokyo   [Invited Talk] Low power Deep Learning hardware using emerging analog non-volatile memory
Irina Kataeva (DENSO Corp.) 		In recent years, Artificial Intelligence, Deep Learning in particular, has become a hot topic of both research and pract... [more]
SCE 2010-10-19
15:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Demonstration of a 2x2 Single-Flux-Quantum Reconfigurable Data-Path Based on the 10-kA/cm2 Process
Masakazu Okada, Irina Kataeva, Masato Ito, Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki (Nagoya Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Shuuichi Nagasawa (ISTEC), Naofumi Takagi (Kyoto Univ.) SCE2010-33		 We have demonstrated a reconfigurable data-path (RDP) prototype using the single-flux-quantum (SFQ) circuits fabricated ... [more] SCE2010-33
pp.55-60
SCE 2010-07-22
13:40		 Tokyo Kikai-Shinko-Kaikan Bldg. Demonstration of a 4x4 SFQ switch fabricated with the ISTEC 10-kA/cm2 Nb Advanced process 2
Masato Ito, Irina Kataeva, Masakazu Okada, Tomohito Kouketsu, Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki (Nagoya Univ.) SCE2010-21		 We have evaluated the performance of the 4×4 SFQ switch which was designed and fabricated using ISTEC Advanced process ... [more] SCE2010-21
pp.41-46
SCE 2009-10-20
13:25		 Tokyo Kikai-Shinko-Kaikan Bldg. A clock line for a Large Scale Reconfigurable Data Paths Processor
Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki (Nagoya Univ.v) SCE2009-18		 Clocking of the large scale SFQ circuits is a major issue due to accumulated jitter and clock skew that grow with the in... [more] SCE2009-18
pp.7-11
SCE 2006-11-02
14:20		 Aichi Nagoya Univ. RSFQ LSI circuit design approach
Irina Kataeva, Samuel Intiso, Elena Tolkacheva, Anna Kidiyarova-Shevchenko (Chalmers University of Technology) 		 [more] SCE2006-26
pp.3-8
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