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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
MW, AP
(Joint)		 2023-09-28
15:50		 Kochi Kochi Castle Museum of History
(Primary: On-site, Secondary: Online)		 Study on Design of WRG with Low-loss and Wideband Characteristics
Masatora Ueno (Utsunomiya Univ.), Yutaka Aoki, Hitoshi Tanaka, Kamo Hiroyuki (TAIYO YUDEN), Takashi Shimizu (Utsunomiya Univ.) MW2023-84		 A WRG transmission line (Waffle-Iron Ridge Guide) will expect for the next generation of wireless communication technolo... [more] MW2023-84
pp.16-21
OME 2014-10-10
11:20		 Osaka Osaka University Nakanoshima Center Emission Properties of Bilayer Organic Light-Emitting Transistors Doped with Phosphorescent Dyes
Hirotake Kajii, Hitoshi Tanaka, Ikuya Ikezoe, Mikio Hara, Takahiro Ohtomo, Yutaka Ohmori (Osaka Univ.) OME2014-39		 The fabrication and characteristics of top-gate type bilayer polymer light-emitting transistors with phosphorescent dye ... [more] OME2014-39
pp.9-13
OME 2013-10-11
13:40		 Osaka Osaka Univ. Nakanoshima Center Interface Effect of Insulator/Active Layer on Fluorene-type Organic Light-emitting Transistor Characteristics with Polymer Gate Insulator
Masato Ise, Ikuya Ikezoe, Koichi Hiraoka, Hitoshi Tanaka, Hirotake Kajii, Yutaka Ohmori (Osaka Univ.) OME2013-59		  [more] OME2013-59
pp.45-48
ICD 2006-04-13
10:10		 Oita Oita University An 8.4ns Column-Access 1.6Gb/s/pin DDR3 SDRAM with an 8:4 Multiplexed Data-Transfer Scheme
Shuichi Kubouchi (Hitachi ULSI), Hiroki Fujisawa, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda (Elpida Memory), Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka (Hitachi ULSI), Masayuki Nakamura (Elpida Memory) 		The column access time of a 512Mb DDR3 SDRAM made by a 90nm dual-gate CMOS process is reduced by 2.9ns to 8.4ns through ... [more] ICD2006-3
pp.13-18
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