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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
COMP 2016-10-21
Miyagi Tohoku University A Research of the Number of the Convex Configurations of Silhouette Puzzles
Hitoshi Iwai, Jungo Shibuya, Ryuhei Uehara (JAIST) COMP2016-29
(To be available after the conference date) [more] COMP2016-29
DC, CPSY 2015-04-17
Tokyo   A Proposal of Time-Lag-Less n-Fault-Tolerant Control System
Hitoshi Iwai CPSY2015-3 DC2015-3
In a conventional multi-modular majority voting redundancy for real-time hazard control the first processing step is tha... [more] CPSY2015-3 DC2015-3
DC 2014-12-19
Toyama   A Proposal of Fault-Mask Triple Modular Redundancy with Certification and Integrity-check Code
Hitoshi Iwai DC2014-71
It must prove that output data of a function module and that of another function module are the same to check an integri... [more] DC2014-71
(Joint) [detail]
Oita B-ConPlaza Some Studies of n-Fault-Tolerant System with Voting Switches
Hitoshi Iwai VLD2014-111 DC2014-65
This paper proposes n-fault-tolerant system method of voting redundancy with multiplied function modules. In well-known ... [more] VLD2014-111 DC2014-65
ICD 2008-04-17
Tokyo   [Invited Talk] An 833MHz Pseudo Two-Port Embedded DRAM for Graphics Applications
Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka (Toshiba) ICD2008-3
This paper describes a pseudo two-port embedded DRAM macro developed for graphics applications. It introduces read/write... [more] ICD2008-3
ICD 2006-04-13
Oita Oita University A 65nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode
Tomohisa Takai, Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Naoko Itoga, Takayuki Miyazaki (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano (Toshiba)
An Extended Data Retention (EDR) sleep mode with on-chip ECC and the MT-CMOS technique is proposed for the embedded DRAM... [more] ICD2006-2
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