IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 13 of 13  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RISING
(2nd)
2019-11-27
13:55
Tokyo Fukutake Learning Theater, Hongo Campus, Univ. Tokyo [Poster Presentation] Battery-powered arrhythmia detection system implemented in low-power FPGA device
Yuji Yano (Osaka City Univ./PCN), Hisashi Iwamoto, Takuma Yoshimura (PCN), Kazutami Arimoto (Okayama PU), Shingo Ata (Osaka City Univ.)
 [more]
RECONF 2016-09-06
13:25
Toyama Univ. of Toyama A Memory Based Realization of the Binarized Deep Convolutional Neural Network
Hiroki Nakahara, Haruyoshi Yonekawa (TITECH), Tsutomu Sasao (Meiji Univ.), Hisashi Iwamoto (Poco a poco Networks), Masato Motomura (Hokkaido Univ.) RECONF2016-37
 [more] RECONF2016-37
pp.63-68
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-21
14:55
Kanagawa Hiyoshi Campus, Keio University A Realization of Deep Convolutional Neural Network using the Nested RNS on an FPGA including the Constant Division
Hiroki Nakahara (Ehime Univ.), Tsutomu Sasao (Meiji Univ.), Hisashi Iwamoto (REVSONIC Corp.) VLD2015-108 CPSY2015-140 RECONF2015-90
 [more] VLD2015-108 CPSY2015-140 RECONF2015-90
pp.227-232
IN, NV
(Joint)
2015-07-17
10:40
Hokkaido Hokkaido University Implementation and Evaluation of Energy-aware Search Hardware Applicable to Wide and Sparse Rules
Keiko Endo, Masami Nawa, Shingo Ata (Osaka City Univ.), Yuji Yano, Yasuto Kuroda (Renesas), Hisashi Iwamoto (REVSONIC), kazunari Inoue (Nara National College of Tec./Osaka Univ.), Ikuo Oka (Osaka City Univ.) IN2015-33
TCAM (Ternary Content Addressable Memory) is widely used as a search hardware for high speed table lookups.
However, TC... [more]
IN2015-33
pp.61-66
IN 2014-04-18
14:15
Kyoto Kyotofu-Chusho-Kigyo-Kaikan Low-Power and High-Speed Search Engine by Multi-dimensional TCAM Architecture with Parallel Pipelined Subdivided Structure
Kenzo Okuda, Masami Nawa, Shingo Ata (Osaka City Univ.), Yuji Yano, Yasuto Kuroda (Renesas), Hisashi Iwamoto (REVSONIC), kazunari Inoue (Nara National College of Tec./Osaka Univ.), Ikuo Oka (Osaka City Univ.) IN2014-7
TCAM (Ternary Content Addressable Memory) is widely used for high speed searching applications on networking equipment. ... [more] IN2014-7
pp.67-72
NS, IN
(Joint)
2013-03-07
10:50
Okinawa Okinawa Zanpamisaki Royal Hotel Parameters to Minimize an Energy Overhead of Two Dimensional Sliced Packet Buffer
Kenzo Okuda, Shingo Ata (Osaka City Univ.), Yuji Yano, Yasuto Kuroda (Renesas Electronics), Hisashi Iwamoto (Osaka City Univ.), kazunari Inoue (Nara National College of Tec./Osaka Univ.), Ikuo Oka (Osaka City Univ.) IN2012-155
Recently, energy consumption of routers has become a serious problem, hence power reduction is an urgent challenge. In p... [more] IN2012-155
pp.7-12
ICD 2012-12-17
14:20
Tokyo Tokyo Tech Front A 250Msps, 0.5W eDRAM-based Search Engine applying full-route capacity dedicated FIB application
Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto (Renesas), Koji Yamamoto (RDC), kazunari Inoue (Nara National College of Tech./Osaka Univ.) ICD2012-91
 [more] ICD2012-91
pp.21-26
CQ, ICM, NS
(Joint)
2012-11-16
13:10
Shiga Nagahama Inst. of Bio-Science and Tech. [Encouragement Talk] Latency Reduction in Energy-aware Routers Using Grained Traffic Prediction
Sou Koyano, Shingo Ata, Hisashi Iwamoto (Osaka City Univ.), Yuji Yano, Yasuto Kuroda (Renesas), kazunari Inoue (Nara National College of Tech./Osaka Univ.), Ikuo Oka (Osaka City Univ.) NS2012-111
We have proposed Sliced Router Architecture, which reduces the power consumption of routers by adjusting routers' perfor... [more] NS2012-111
pp.41-46
IN, RCS
(Joint)
2012-05-18
14:50
Tokyo Kuramae-Kaikan, Tokyo Institute of Technology Performance Evaluation on Energy Consumption of Sliced Packet Buffer with Traffic Volume and Occupancy Adaptation
Kenzo Okuda, Shingo Ata (Osaka City Univ.), Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto (Renesas), kazunari Inoue (Nara National College of Tec./Osaka Univ.), Ikuo Oka (Osaka City Univ.) IN2012-19
Recently, energy consumption of routers is becoming a problem so power reduction becomes urgent and important challenge.... [more] IN2012-19
pp.43-48
NS, IN
(Joint)
2012-03-09
14:10
Miyazaki Miyazaki Seagia A Memory Controller with Guaranteed-Bandwidth Solution
Hisashi Iwamoto, Yasuto Kuroda, Yuji Yano (Renesas), Koji Yamamoto (RDC), Shingo Ata (Osaka City Univ.), kazunari Inoue (Nara National College of Tec./Osaka Univ.) NS2011-258
Network traffic keeps increasing like as the demand of video streaming. Routers and switches in wire-line networks requi... [more] NS2011-258
pp.445-450
NS, IN
(Joint)
2012-03-09
14:30
Miyazaki Miyazaki Seagia Advanced memory controller for Low power router architecture
Yasuto Kuroda, Hisashi Iwamoto, Yuji Yano (Renesas), Shiro Otani (Hitachi Info. & Comm. Eng.), Kenzo Okuda, Shingo Ata (Osaka City Univ.), kazunari Inoue (Nara National College of Tech./Osaka Univ.), Go Hasegawa, Masayuki Murata (Osaka Univ.) NS2011-259
The complete network service of infrastructure is an urgent issue by means of continuous growth in network traffic. Appa... [more] NS2011-259
pp.451-455
IN, NS
(Joint)
2011-03-03
09:40
Okinawa Okinawa Convention Center A Router Architecture comprises plural components of Slice enabling Energy Consumption Reduction
Hisashi Iwamoto, Kazunari Inoue (Renesas), Shingo Ata (Osaka City Univ.), Shiro Otani (Hitachi Info. & Comm. Eng.), Go Hasegawa (Osaka Univ.), Yuji Yano, Yasuto Kuroda (Renesas), Masayuki Murata (Osaka Univ.) NS2010-186
The complete network service of infrastructure is an urgent issue by means of continuous growth in network traffic. Appa... [more] NS2010-186
pp.129-134
ICD, SDM 2009-07-16
11:25
Tokyo Tokyo Institute of Technology Low Energy Building Design in Packet Buffer Architecture with Deterministic Performance Guarantee
Kazuya Zaitsu (Osaka City Univ.), Hisashi Iwamoto, Yasuto Kuroda, Yuji Yano (Renesas Technology), Koji Yamamoto (Renesas Design), Kazunari Inoue (Renesas Technology), Shingo Ata, Ikuo Oka (Osaka City Univ.) SDM2009-100 ICD2009-16
To design guaranteed high-performance router, it is problem that packet buffer is non-deterministic. We propose Head Buf... [more] SDM2009-100 ICD2009-16
pp.17-22
 Results 1 - 13 of 13  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan