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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 23件中 1~20件目  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2019-03-18
09:00
Kagoshima Nishinoomote City Hall (Tanega-shima) A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem
Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] CPSY2018-117 DC2018-99
pp.315-320
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
13:00
Hiroshima Satellite Campus Hiroshima Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
3D die-stacking technique using TSVs has gained much attention as a new integration method of IC.
However, faulty TSVs ... [more]
VLD2018-56 DC2018-42
pp.119-124
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
13:50
Hiroshima Satellite Campus Hiroshima Study on the Applicability of ATPG Pattern for DFT Circuit
Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
With high integration of IC, small delay faults have occurred as the cause of a circuit failure. As a design-for-testabi... [more] VLD2018-58 DC2018-44
pp.131-136
DC 2018-02-20
10:35
Tokyo Kikai-Shinko-Kaikan Bldg. Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
TSV attracts attention as a new implementation method of interconnects between dies in 3DICs.
However, faulty TSVs may ... [more]
DC2017-79
pp.13-18
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
11:20
Kumamoto Kumamoto-Kenminkouryukan Parea Design to Improve Open Defect Detection for Test Based on IDDT Appearance Time
Ayumu Kambara, Kouhei Ohtani, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
Increasing open defects has become a problem.
We proposed a supply current test method with a built-in sensor for dete... [more]
VLD2017-49 DC2017-55
pp.125-130
DC 2017-02-21
14:25
Tokyo Kikai-Shinko-Kaikan Bldg. An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States
Morito Niseki, Toshinori Hosokawa (Nihon Univ.), Msayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
Scan design has problems such as large hardware overhead and long test application time. Non-scan based test generation ... [more] DC2016-79
pp.29-34
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-30
09:25
Osaka Ritsumeikan University, Osaka Ibaraki Campus Design of TDC Embedded in Scan FFs for Testing Small Delay Faults
Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures.
... [more]
VLD2016-62 DC2016-56
pp.105-110
DC 2016-02-17
10:50
Tokyo Kikai-Shinko-Kaikan Bldg. Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value
Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
As semiconductor technology is scaling down, open defects have often occurred at interconnect lines and vias. If logic v... [more] DC2015-88
pp.13-18
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-01
14:40
Nagasaki Nagasaki Kinro Fukushi Kaikan On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines
Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
The effect of a resistive open results in small delay in an IC. It is difficult to test small delay since signal delay a... [more] VLD2015-42 DC2015-38
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
14:45
Oita B-ConPlaza Investigation of the area reduction of observation part and control part in TSV fault detection circuit
Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
Since delay caused by an open TSV is usually very small, it is defficult to detect. Therefore, we have proposed a TSV fa... [more] VLD2014-72 DC2014-26
pp.3-8
DC 2014-02-10
09:25
Tokyo Kikai-Shinko-Kaikan Bldg. On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan
Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima)
In recent deep sub-micron (DSM) ICs, it is difficult to detect open and
short defects since they do not behave like co... [more]
DC2013-80
pp.7-12
DC 2014-02-10
15:35
Tokyo Kikai-Shinko-Kaikan Bldg. Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift and Partial Reset of Inverter Code
Ryota Mori, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima)
BIST-aided scan test (BAST) has been proposed as one of the techniques that enhances scan-based BIST. The BAST architect... [more] DC2013-88
pp.55-60
DC 2013-02-13
13:30
Tokyo Kikai-Shinko-Kaikan Bldg. Characteristic Analysis of Signal Delay for Resistive Open Fault Detection
Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistiv... [more] DC2012-84
pp.25-30
DC 2013-02-13
13:55
Tokyo Kikai-Shinko-Kaikan Bldg. On Fault detection method considering adjacent TSVs for a delay fault in TSV
Masanori Nakamura, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ.of Tokushima)
We propose a fault detection method for a TSV (through-Silicon via) considering adjacent TSVs for detecting delay caused... [more] DC2012-85
pp.31-36
DC 2012-06-22
14:20
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg [Invited Talk] Empirical study for signal integrity-defects
Hiroshi Takahashi, Yoshinobu Higami (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. Tokushima)
We try to empirically study signal integrity-defects.
In this study, we analyze the resistive open fault that causes th... [more]
DC2012-12
pp.21-26
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-29
10:15
Miyazaki NewWelCity Miyazaki A BIST-Aided Scan Test using Shifting Inverter Code and a TPG Method for Test Data Reduction
Yasuhiko Okada, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima)
BIST-aided scan test (BAST) has been proposed as one of the techniques that enhance scan-based BIST.The BAST architectur... [more] VLD2011-74 DC2011-50
pp.133-138
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-30
10:30
Miyazaki NewWelCity Miyazaki On the design for testability method using Time to Digital Converter for detecting delay faults
Hiroyuki Makimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima)
We propose the design for testability method for detecting delay fault that can form a TDC(Time-to-Digital Converter) to... [more] VLD2011-84 DC2011-60
pp.185-190
DC 2010-02-15
10:25
Tokyo Kikai-Shinko-Kaikan Bldg. Modeling resistive open faults and generating their tests
Hiroshi Takahashi, Yoshinobu Higami, Yuta Shudo, Yuji Takamune, Yuzo Takamatsu (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima)
In order to solve the problem of signal integrity, we propose an extended delay fault model for modeling a resistive ope... [more] DC2009-68
pp.19-24
DC 2010-02-15
16:05
Tokyo Kikai-Shinko-Kaikan Bldg. Consideration of Open Faults Model Based on Digital Measurement of TEG Chip
Toshiyuki Tsutsumi (Meiji Univ.), Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ)
Countermeasures against an open fault in LSI testing become more important with advancement of LSI process technology. ... [more] DC2009-77
pp.75-80
DC 2009-02-16
14:15
Tokyo   On Tests to Detect Open faults with Considering Adjacent Lines
Tetsuya Watanabe, Hiroshi Takahashi, Yoshinobu Higami (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ, Tokushima), Yuzo Takamatsu (Ehime Univ.)
In modern manufacturing technologies with the shrinking of manufacturing process, LSIs may have several metal interconne... [more] DC2008-74
pp.37-42
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