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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2011-04-19
10:20
Hyogo Kobe University Takigawa Memorial Hall Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs
Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Kiyoshi Takeuchi, Masahiro Nomura, Yoshihiro Hayashi (Renesas Electronics) ICD2011-10
 [more] ICD2011-10
pp.55-58
ICD 2006-04-14
11:40
Oita Oita University Redefinition of Write Margin for Next-Generation SRAMs and Write-Margin Monitoring Circuits
Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura (NEC), Hiroyuki Kobatake (NECEL)
 [more] ICD2006-16
pp.85-90
ICD 2005-04-14
09:00
Fukuoka   A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications
Koichi Takeda, Yasuhiko Hagihara (NEC), Yoshiharu Aimoto (NECEL), Masahiro Nomura, Yoetsu Nakazawa (NEC), Toshio Ishii, Hiroyuki Kobatake (NECEL)
A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-Vt NMOS transistors us... [more] ICD2005-1
pp.1-6
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