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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| QIT (2nd) |
2023-12-17 17:30 |
Okinawa | OIST (Primary: On-site, Secondary: Online) |
[Poster Presentation]
Effects of physical noise on hybrid tensor networks Hiroyuki Harada (Keio), Yasunari Suzuki (NTT), Bo Yang (Sorbonne), Yuuki Tokunaga, Suguru Endo (NTT) |
[more] | |
| OME, SDM | 2017-04-21 14:05 |
Kagoshima | Tatsugochou Shougaigakushuu Center | Charge storage behavior of zirconia ceramics under DC electric field
-- Preparation of Y-TZP bioceramics with enhanced LTD durability -- Yumi Tanaka (Tokyo Univ. of Sci.), Hiroyuki Hara (Kyushu Univ.)  SDM2017-8 OME2017-8 |
Yttria-stabilized tetragonal zirconia polycrystal (Y-TZP) is an important load-bearing bioceramic. However, a phenomenon... [more] | SDM2017-8 OME2017-8 pp.35-39 |
| SDM | 2016-01-28 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126 |
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] | SDM2015-126 pp.27-30 |
| SDM, ICD | 2015-08-24 10:55 |
Kumamoto | Kumamoto City | [Invited Talk]
Implementation of TFET Spice Model for Ultra-Low Power Circuit Analysis Chika Tanaka, Akira Hokazono, Kanna Adachi, Masakazu Goto, Yoshiyuki Kondo, Emiko Sugizaki, Motohiko Fujimatsu, Hiroyuki Hara, Shinji Miyano, Keiichi Kushida, Shigeru Kawanaka (Toshiba) SDM2015-59 ICD2015-28 |
[more] | SDM2015-59 ICD2015-28 pp.11-13 |
| ICD | 2015-04-17 12:40 |
Nagano | [Invited Talk]
Low-power Embedded Perpendicular STT-MRAM Design for Cache Memory Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Chika Tanaka, Chikayoshi Kamata, Minoru Amano, Eiji Kitagawa, Naoharu Shimomura, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) ICD2015-10 |
[more] | ICD2015-10 pp.45-50 |
|
| SDM | 2015-01-27 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2014-142 |
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, ... [more] | SDM2014-142 pp.29-32 |
| ISEC, IT, WBS | 2011-03-04 09:00 |
Osaka | Osaka University | Construction of non-hyperelliptic coverings for elliptic curves on extension fields Hiroyuki Hara (Chuo Univ.), Tsutomu Iijima, Mahoro Shimura (Tokai Univ.), Jinhui Chao (Chuo Univ.) IT2010-92 ISEC2010-96 WBS2010-71 |
The GHS attack transfers the discrete logarithm problem(DLP) in the group of rational points of an elliptic curve over a... [more] | IT2010-92 ISEC2010-96 WBS2010-71 pp.143-150 |
| SCE, MW | 2010-04-23 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Experimental study of bandwidth tunable filters using Π-shaped waveguides Naoto Sekiya, Hiroyuki Harada, Yasuhiko Nakagawa (Yamanashi Univ.), Shigetoshi Ohshima (Yamagata Univ.) SCE2010-7 MW2010-7 |
We have developed a method for tuning the bandwidth of microstrip filter. Several -shaped waveguides are placed ... [more] | SCE2010-7 MW2010-7 pp.33-37 |
| MW, SCE | 2009-04-23 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Study of bandwidth tunable HTS filters using H-shaped waveguides Naoto Sekiya, Yusuke Koike, Hiroyuki Harada, Shoji Kakio, Yasuhiko Nakagawa (Yamanashi Univ.), Shigetoshi Ohshima (Yamagata Univ.) SCE2009-6 MW2009-6 |
We have developed a bandwidth tuning method for use in high-temperature superconducting (HTS) microstrip filters. Severa... [more] | SCE2009-6 MW2009-6 pp.29-34 |
| SDM | 2007-12-14 17:00 |
Nara | Nara Institute Science and Technology | Neural Network of Device Level using Poly-Si TFT Ryo Onodera, Tomohiro Kasakawa, Hiroki Kojima, Mutsumi Kimura (Ryukoku Univ.), Hiroyuki Hara, Satoshi Inoue (Seiko Epson Corp.) SDM2007-235 |
We have developed a neural network of device level using TFT. Extreamly simplified circuit configulation is achieved usi... [more] | SDM2007-235 pp.55-58 |
| ED, SDM | 2007-06-25 13:00 |
Overseas | Commodore Hotel Gyeongju Chosun, Gyeongju, Korea | [Invited Talk]
Requirements for Thin Film Transistor Circuits on Plastic Mitsutoshi Miyasaka, Hiroyuki Hara, Nobuo Karaki, Satoshi Inoue (Seiko Epson) |
The self-heating effect of thin film transistors (TFTs) is a serious problem when the TFT circuits are formed on a plast... [more] | |
| ICD | 2005-12-16 10:50 |
Kochi | A Conditional Clocking Flip-Flop for Low Power H.264/MPEG-4 Audio/Visual Codec LSI Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Masafumi Takahashi, Yukihito Oowaki (Toshiba Corp.) |
A novel conditional clocking flip-flop is proposed. The flip-flop circuit does not consume any power when the data inpu... [more] | ICD2005-196 pp.25-29 |
|
| ICD | 2005-05-26 11:00 |
Hyogo | Kobe Univ. | An H.264/MPEG-4 Audio/Visual Codec LSI with Module-Wise Dynamic Voltage/Frequency Scaling Yoshiyuki Kitasho, Toshihide Fujiyoshi, Shinichiro Shiratake, Tsuyoshi Nishikawa, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Masafumi Takahashi, Yukihito Oowaki (TOSHIBA) |
A single-chip MPEG-4 audiovisual LSI with ability of CIF 15fps encoding is fabricated in a 0.13um CMOS, 5-layer metal te... [more] | ICD2005-22 pp.13-18 |
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