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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2015-04-16
13:25		 Nagano   [Invited Lecture] A 512-kb 1-GHz 28-nm Partially Write Assisted Dual-Port SRAM with Self Adjustable Negative Bias Bitline
Shinji Tanaka (Renesas Electronics), Yuichiro Ishii, Makoto Yabuuchi (Renesas), Toshiaki Sano (Renesas System Design), Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato (Renesas) ICD2015-2		  [more] ICD2015-2
pp.5-8
ICD, ITE-CE 2007-12-13
16:25		 Kochi   A new SRAM memory cell with small cell ratio using dynamic stability
Yuji Kihara (Renesas Technology), Yutaka Arita (Fujita Health University Collage), Leona Okamura (Waseda University Graduated School), Hirotoshi Sato (Renesas Technology), Tsutomu Yoshihara (Waseda University Graduated School) ICD2007-126		  [more] ICD2007-126
pp.37-40
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