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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MBE, NC | 2022-12-03 16:40 |
Osaka | Osaka Electro-Communication University | Correlation-based discretization method of continuous variables in annealing machines Yuki Furue (Saitama Univ.), Makiko Konoshima (Fujitsu), Hirotaka Tamura (DXR Lab. Inc.), Jun Ohkubo (Saitama Univ.)  MBE2022-42 NC2022-64 |
Recently, annealing hardware specialized to combinatorial optimization problems has been developed, and there are some s... [more] | MBE2022-42 NC2022-64 pp.98-103 |
| MBE, NC (Joint) |
2021-10-29 11:15 |
Online | Online | Visualization and quantification of the difficulty of combinatorial optimization problems in Ising formulation Keiichi Soejima (Saitama Univ.), Makiko Konoshima, Hirotaka Tamura (Fujitsu), Jun Ohkubo (Saitama Univ.) NC2021-25 |
With the aim of rapidly solving combinatorial optimization problems, dedicated hardware using the Ising Model is being d... [more] | NC2021-25 pp.40-45 |
| NC, MBE (Joint) |
2019-03-04 11:10 |
Tokyo | University of Electro Communications | Numerical experiments of QUBO formulation for ReLU-type functions Go Sato (Saitama Univ.), Makiko Koreshima, Takuya Owa, Hirotaka Tamura (Fujitsu Labs), jun Ohkubo (Saitama Univ.) NC2018-52 |
[more] | NC2018-52 pp.49-54 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 13:30 |
Oita | B-ConPlaza | [Invited Talk]
A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS Yasufumi Sakai, Takayuki Shibasaki, Takumi Danjo, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura (Fujitsu LAB.) VLD2014-96 CPM2014-127 ICD2014-70 CPSY2014-84 DC2014-50 RECONF2014-45 |
To meet ever-increasing demands for computing power in data centers, data rates over 50Gbps/signal (e.g., OIF CEI-56G-VS... [more] | VLD2014-96 CPM2014-127 ICD2014-70 CPSY2014-84 DC2014-50 RECONF2014-45 pp.167-172(VLD), pp.27-32(CPM), pp.27-32(ICD), pp.69-74(CPSY), pp.167-172(DC), pp.63-68(RECONF) |
| ICD, ITE-IST | 2013-07-04 10:55 |
Hokkaido | San Refre Hakodate | [Invited Talk]
32 Gb/s Data-Interpolator Receiver with 2-tap DFE in 28-nm CMOS Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida (Fujitsu Lab. Ltd.), Hiroki Miyaoka (FSL), Masanori Hoshino (FMSL), Yoichi Koyanagi (Fujitsu Lab. Ltd.), Takuji Yamamoto (FLA), Sanroku Tsukamoto, Hirotaka Tamura (Fujitsu Lab. Ltd.) ICD2013-27 |
We present a 32Gb/s data-interpolator receiver for electrical chip-to-chip communications. The receiver front-end is clo... [more] | ICD2013-27 pp.19-24 |
| CAS, NLP | 2011-10-21 14:05 |
Shizuoka | Shizuoka Univ. | [Invited Talk]
Receiver Front-End Design for CMOS High-Speed I/O Masaya Kibune, Hirotaka Tamura, Takuji Yamamoto (FLL) CAS2011-56 NLP2011-83 |
A CMOS transceiver macro for wire-line communication is required to operate at higher data rate and to be compatible wit... [more] | CAS2011-56 NLP2011-83 pp.135-140 |
| ICD, SDM | 2006-08-17 16:10 |
Hokkaido | Hokkaido University | A 20-GHz Injection-Locked LC Divider with a 25-% Locking Range Takayuki Shibasaki (Keio Univ.), Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa (Fujitsu Laboratories LTD.), Tadahiro Kuroda (Keio Univ.) |
[more] | SDM2006-138 ICD2006-92 pp.75-79 |
| ICD | 2006-05-26 16:15 |
Hyogo | Kobe University | A 20Gb/s Bidirectional Transceiver Using a Resister-Transconductor Hybrid Yasumoto Tomita (Keio Univ.), Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh (Fujitsu Laboratories LTD.), Tadahiro Kuroda (Keio Univ.) |
This paper presents a 20-Gb/s simultaneous bidirectional transceiver using a resistor-transconductor (R-gm) hybrid in a ... [more] | ICD2006-39 pp.101-104 |
| ICD | 2005-12-16 13:50 |
Kochi | A 0.8-1.3V 16-channel 2.5Gbps High-speed Serial Transceiver in a 90nm Standard CMOS Process Yoshiyasu Doi (Fujitsu Labs.), Syunitirou Masaki, Takaya Chiba (Fujitsu), Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida (Fujitsu Labs.), Kohtaroh Gotoh (Fujitsu), Junji Ogawa, Hirotaka Tamura (Fujitsu Labs.) |
We describe a 16-channel 2.5Gb/s low-power transceiver that operates off a single supply voltage ranging from 0.8V to 1.... [more] | ICD2005-201 pp.55-60 |
|
| VLD, ICD, DC, IPSJ-SLDM | 2005-11-30 14:40 |
Fukuoka | Kitakyushu International Conference Center | 40-Gbps 4:1 MUX/1:4 DEMUX in 90-nm standard CMOS technology Kouichi Kanda, Daisuke Yamazaki, Takuji Yamamoto, Minoru Horinaka, Junji Ogawa, Hirotaka Tamura, Hiroyuki Onodera (Fujitsu Labs.) |
[more] | VLD2005-55 ICD2005-150 DC2005-32 pp.7-14 |
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