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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2011-03-02
14:25		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Intra-task Analysis of Worst Case Execution Time and Average Energy Consumption on DEPS Framework
Hirotaka Kawashima, Gang Zeng, Noritoshi Atsumi, Tomohiro Tatematsu, Hiroaki Takada (Nagoya Univ.) VLD2010-119		 In this paper, we show an intra-task average energy consumption(AEC) and worst case execution time(WCET) analysis. The ... [more] VLD2010-119
pp.19-24
VLD 2010-03-12
13:05		 Okinawa   Estimating Signal Transition Frequency of Arithmetic Circuits Using Cell Delay Model
Hirotaka Kawashima, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) VLD2009-124		  [more] VLD2009-124
pp.151-156
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2009-12-04
15:00		 Kochi Kochi City Culture-Plaza Evaluation of Energy Consumption on Multipliers Using the Sum of Operands
Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ.) VLD2009-66 DC2009-53		 We evaluate dynamic energy consumption of multipliers using the sum of operands we have proposed before.
The multiplie... [more]		 VLD2009-66 DC2009-53
pp.173-178
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2008-11-17
15:00		 Fukuoka Kitakyushu Science and Research Park Area Efficient Multipliers Utilizing the Sum of Operands
Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ.) VLD2008-64 DC2008-32		 A method to halve the number of partial product bits in multiplication is proposed. An integrated partial product (IPP) ... [more] VLD2008-64 DC2008-32
pp.25-30
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-21
16:10		 Fukuoka Kitakyushu International Conference Center Design of low energy array multipliers by reducing signal transitions in partial product accumulators
Hirotaka Kawashima, Kazuhiro Nakamura, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) VLD2007-87 DC2007-42		 We propose a method to reduce energy consumption of array multipliers by reducing the number of signal transitions.
In ... [more]		 VLD2007-87 DC2007-42
pp.31-36
ICD, VLD 2007-03-09
09:00		 Okinawa Mielparque Okinawa Effect of the Number of Wiring Layers on the Chip Area of Multipliers
Hirotaka Kawashima, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) 		The number of metal layers usable for wiring is increasing because of the progress of manufacturing technologies of VLSI... [more] VLD2006-141 ICD2006-232
pp.7-11
 Results 1 - 6 of 6  /   
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