IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DE, IPSJ-DBS, IPSJ-IFAT [detail] 2023-09-22
11:20
Fukuoka Kitakyushu International Conference Center A prototype system for interactively combining more than 1000 pieces of table formatted big data and interactively overviewing of it -- Performance measurement of overviewing (displaying, searching, tabulating, and sorting) more than 3 trillion records of virtual table formatted data --
Shinji Furusho (NNI Technologies), Atsushi Iizawa (Ricoh IT Solutions), Hiroshi Tezuka (Bird's-eye View Engineering Institute), Yukio Yamamoto (ISAS), Takashi Matsuhisa, Manabu Iida (SEC), Tadashi Nagao (Layman's Admin) DE2023-24
The virtual tabular data, created with the purpose of facilitating the distribution of diverse tabular big data, is a vi... [more] DE2023-24
pp.78-83
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2020-02-27
17:00
Kagoshima Yoron-cho Chuou-Kouminkan HLS by multi-objective optimization under resource constraints -- Approach to extracting coarse-grained parallelism using functional language --
Fukuhei Hamazaki, Tetsuro Yamazaki, Ryota Shioya (U-Tokyo), Kenichi Koizumi, Hiroshi Tezuka, Mary Inaba (U-Tokyo) CPSY2019-104 DC2019-110
For engineers who are not familiar with circuits, it is difficult to optimize circuit considering trade-off factors such... [more] CPSY2019-104 DC2019-110
pp.99-104
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2019-03-18
09:20
Kagoshima Nishinoomote City Hall (Tanega-shima) Problems of High Level Synthesis for software developers -- Comparison between RTL and HLS in a FPGA Othello game system --
Fukuhei Hamazaki, Hiroshi Tezuka, Mary Inaba (Tokyo Univ.) CPSY2018-112 DC2018-94
 [more] CPSY2018-112 DC2018-94
pp.227-232
NC, MBE
(Joint)
2018-12-15
14:50
Aichi Nagoya Institute of Technology Multi-Abstraction-Level Feature Extractor toward General Features -- Utilization of Patterns in Intermediate Bidirectional Layers --
Kaneharu Nishino, Hiroshi Tezuka, Mary Inaba (Tokyo Univ.) NC2018-35
 [more] NC2018-35
pp.41-46
IBISML 2016-11-16
15:00
Kyoto Kyoto Univ. Algorithm for Detecting Overlapped Communities in Networks
Kiyotaka Mori, Kaneharu Nishino, Hiroshi Tezuka, Mary Inaba (UTokyo) IBISML2016-66
The Community is defined as the set of nodes which is densely connected internally in complex networks. The existing Ext... [more] IBISML2016-66
pp.143-150
VLD 2014-03-04
09:40
Okinawa Okinawa Seinen Kaikan An Effective Solution Space for Simulated Annealing
Hiroshi Tezuka, Kunihiro Fujiyoshi (TUAT) VLD2013-143
Simulated Annealing is a universal probabilistic metaheuristic for the general optimization problem of locating a good a... [more] VLD2013-143
pp.55-60
 Results 1 - 6 of 6  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan