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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2024-04-12
13:25
Kanagawa
(Primary: On-site, Secondary: Online)
[Invited Lecture] 5-Bit/2Cell(X2.5), 7-Bit/2Cell(X3.5), 9-Bit/2Cell(X4.5) NAND Flash Memory: Half Bit technology
Noboru Shibata, Hironori Uchikawa, Taira Shibuya, Kenri Nakai, Kosuke Yanagidaira, Kosuke Yanagidaira (KIOXIA)
(To be available after the conference date) [more]
IT 2015-07-14
11:20
Tokyo Tokyo Institute of Technology Maximization of Number of Rewritings for Index-less Indexed Flash Codes with Bits for Reversal
Akira Yamawaki (Gifu Univ.), Hironori Uchikawa (Toshiba), Hiroshi Kamabe (Gifu Univ.) IT2015-32
The index-less indexed flash code(ILIFC) with bits for reversal is a variant of a coding scheme proposed by Mahdavifar e... [more] IT2015-32
pp.89-94
IT 2011-09-29
14:40
Tokyo Tokyo Institute of Technology Spatially Coupled Low Density Lattice Codes
Hironori Uchikawa (Tokyo Inst. of Tech.), Brian M. Kurkoski (Univ. of Electro-Comm.), Kenta Kasai, Kohichi Sakaniwa (Tokyo Inst. of Tech.) IT2011-25
Spatially-coupled low-density lattice codes
(LDLC) are constructed using protographs.
Using Monte Carlo density evol... [more]
IT2011-25
pp.9-14
IT 2011-09-30
11:10
Tokyo Tokyo Institute of Technology Efficient Encoding for Quasi-Cyclic LDPC Codes with Rank Deficient Parity Check Matrices
Haruka Obata, Hironori Uchikawa (Toshiba) IT2011-29
This paper presents an efficient encoding method for quasi-cyclic low-density parity-check (QC-LDPC) codes with rank def... [more] IT2011-29
pp.35-40
IT 2010-09-21
15:45
Miyagi Tohoku Gakuin University Performance and Construction of Rate-Compatible Non-Binary LDPC Convolutional Codes
Hironori Uchikawa, Kenta Kasai, Kohichi Sakaniwa (Tokyo Inst. of Tech.) IT2010-37
In order to establish reliable communication systems over channels with wide range of noise strength,
it is desired to... [more]
IT2010-37
pp.19-24
IT 2008-09-11
17:55
Okinawa Culture Resort Festone (Okinawa) Complexity-reducing Algorithm for Serial Min-sum Decoding
Hironori Uchikawa, Kohsuke Harada, Yasuhiko Tanabe (Toshiba) IT2008-28
We propose a complexity-reducing algorithm for serial min-sum
decoding that reduces the number of check nodes to proce... [more]
IT2008-28
pp.49-54
 Results 1 - 6 of 6  /   
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