IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 13 of 13  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-11
Online Online LocalMapping Parallelization and CPU Allocation Method on ORB-SLAM3
Kazuki Yamamoto, Takugo Osakabe, Honoka Koike, Tohma Kawasumi, Kazuki Fujita, Toshiaki Kitamura (Waseda Univ.), Akihiro Kawashima, Akira Nodomi (Oscar Tech.), Sadahiro Kimura (NSITEXE,Inc.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2021-58 DC2021-92
(To be available after the conference date) [more] CPSY2021-58 DC2021-92
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-25
Online Online Parallelization and Vectorization of SpMM for Sparse Neural Network
Yuta Tadokoro, Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2020-55 DC2020-85
Pruning is one of the well-known model compression techniques in Deep Learning. Eliminating less important weights in th... [more] CPSY2020-55 DC2020-85
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2020-02-28
Kagoshima Yoron-cho Chuou-Kouminkan Extension of OSCAR Compiler for Parallelizing C++ Programs
Tohma Kawasumi, Tilman Priesner, Masato Noguchi, Jixin Han, Hiroki Mikami (Waseda Univ.), Akihiro Kawashima, Keishiro Tanaka (OscarTechnology Corp.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2019-110 DC2019-116
With the increasing focuses on multicore processors, the OSCAR compiler is known as an automatically parallelizing compi... [more] CPSY2019-110 DC2019-116
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2015-03-07
Kagoshima   Dynamic Scheduling Algorithm for Automatically Parallelized and Power Reduced Applications on Multicore Systems
Takashi Goto, Kohei Muto, Tomohiro Hirano, Hiroki Mikami (Waseda Univ.), Uichiro Takahashi, Sakae Inoue (Fujitsu), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2014-178 DC2014-104
This paper proposes a dynamic scheduling algorithm for multiple automatically parallelized or power reduced applications... [more] CPSY2014-178 DC2014-104
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2014-03-16
Okinawa   A parallelizing compiler cooperative acceleration technique of multicore architecture simulation using a statistical method
Gakuho Taguchi, Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2013-117 DC2013-104
A parallelizing compiler cooperative acceleration technique for multicore architecture simulation is proposed in this pa... [more] CPSY2013-117 DC2013-104
MSS 2010-01-21
Aichi Toyota Central R&D Labs. Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme
Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Satoh (Hitachi), Masayoshi Mase, Jun Shirako (Waseda Univ.), Mikiko Sato (Tokyo Univ. of Agr and Tech.), Masashi Takada, Masayuki Ito (Renesas), Hiroyuki Mizuno (Hitachi), Mitaro Namiki (Tokyo Univ. of Agr and Tech.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CST2009-38
We developed a software-execution framework for scalable increase of execution speed and low-power consumption based on ... [more] CST2009-38
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
Osaka Shoushin Kaikan Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications
Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose core... [more] ICD2008-140
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
Osaka Shoushin Kaikan Local Memory Management Scheme by a Compiler for Multicore Processor
Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
This paper proposes a local memory management scheme for an automatic parallelizing compiler to realize effective use o... [more] ICD2008-141
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
Osaka Shoushin Kaikan A Power Saving Scheme on Multicore Processors Using OSCAR API
Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
Effective power reduction of an application program on multicore processors requires appropriate power control for each ... [more] ICD2008-145
ICD, IPSJ-ARC 2008-05-13
Tokyo   An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping
Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.)
In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which e... [more] ICD2008-20
ICD, IPSJ-ARC 2008-05-14
Tokyo   Automatic Parallelization of Restricted C Programs using Pointer Analysis
Masayoshi Mase (Waseda Univ.), Daisuke Baba (Waseda Univ. / Matsushita Electric Industrial), Harumi Nagayama (Waseda Univ. / Intel), Yuta Murata, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
This paper describes a restriction on pointer usage in C language for parallelism extraction by an automatic parallelizi... [more] ICD2008-30
ICD, SDM 2007-08-23
Hokkaido Kitami Institute of Technology Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding
Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.) SDM2007-143 ICD2007-71
This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processor... [more] SDM2007-143 ICD2007-71
ICD, IPSJ-ARC 2007-05-31
Kanagawa   A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption
Kiyoshi Hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa (Renesas technology), Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka (Hitachi Ltd.), Kiwamu Takada (Hitachi ULSI Systems Co. Ltd.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) ICD2007-22
4320MIPS 4-processor SoC that provides with low power consumption and high performance was designed using 90nm process. ... [more] ICD2007-22
 Results 1 - 13 of 13  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan