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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2023-03-02 14:15 |
Okinawa | (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
DependableHD: A Hyperdimensional Learning Framework for Edge-oriented Voltage-scaled Circuits [Memorial lecture] Dehua Liang (Osaka Univ.), Hiromitsu Awano (Kyoto Univ.), Noriyuki Miura, Jun Shiomi (Osaka Univ.)  VLD2022-93 HWS2022-64 |
Voltage scaling is a promising approach for energy efficiency but also brings challenges to guaranteeing stable circuit ... [more] | VLD2022-93 HWS2022-64 p.111 |
| SeMI, SeMI (Joint) |
2023-01-20 11:15 |
Tokushima | Naruto grand hotel (Primary: On-site, Secondary: Online) |
[Short Paper]
Study of WiFi Beamforming Feedback-Based Respiratory and Heart Rates Estimation Takamochi Kanda, Sota Kondo, Hiroki Shimomura, Takashi Sato, Hiromitsu Awano, Koji Yamamoto (Kyoto Univ.) SeMI2022-99 |
This paper introduces respiration and heart rate estimation based on beamforming feedback (BFF). While BFF has attracted... [more] | SeMI2022-99 pp.131-133 |
| MBE, MICT, IEE-MBE [detail] | 2023-01-17 09:25 |
Saga | Sleep Posture Estimation by Captured Wi-Fi Packets Takayuki Hirai, Hiromitsu Awano, Takashi Sato (Kyoto Univ.) MICT2022-43 MBE2022-43 |
Sleep posture influences sleep quality and is also considered linked to some diseases. Therefore, estimating one's slee... [more] |
MICT2022-43 MBE2022-43 pp.1-6 |
|
| VLD, HWS [detail] | 2022-03-07 13:40 |
Online | Online | [Memorial Lecture]
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification Dehua Liang, Jun Shiomi, Noriyuki Miura (Osaka Univ.), Hiromitsu Awano (Kyoto Univ.) VLD2021-84 HWS2021-61 |
Hyper-Dimensional (HD) computing is a brain-inspired learning approach for efficient and fast learning on today’s embedd... [more] | VLD2021-84 HWS2021-61 p.44 |
| VLD, HWS [detail] | 2022-03-07 15:05 |
Online | Online | Low-Energy and Fast Inference Method for Spiking Neural Networks Using Dynamic Threshold Adjustment Takehiro Habara, Hiromitsu Awano (Kyoto Univ.) VLD2021-87 HWS2021-64 |
Conventional SNNs have fixed thresholds that determine the possibility of neuron firing, resulting in degradation of inf... [more] | VLD2021-87 HWS2021-64 pp.57-62 |
| VLD, HWS [detail] | 2022-03-07 15:30 |
Online | Online | High-throughput In-Memory Accelerator for Binarized Neural Network based on 8T-SRAM Hiroto Tagata, Hiromitsu Awano (Kyoto Univ.) VLD2021-88 HWS2021-65 |
An in-memory accelerator for binary deep neural networks is presented. The proposed circuit doubled the execution spee... [more] |
VLD2021-88 HWS2021-65 pp.63-68 |
| SRW, SeMI, CNR (Joint) |
2021-11-26 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
[Poster Presentation]
Study of Respiratory Rate Estimation Based on WiFi Frame Capture Takamochi Kanda, Takashi Sato, Hiromitsu Awano, Sota, Koji Yamamoto (Kyoto Univ.) SRW2021-44 SeMI2021-43 CNR2021-18 |
This paper introduces a method of respiratory rate estimation based on frame capture of wireless local area network (WLA... [more] | SRW2021-44 SeMI2021-43 CNR2021-18 pp.60-62(SRW), pp.47-49(SeMI), pp.37-39(CNR) |
| ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] | 2019-07-24 13:45 |
Kochi | Kochi University of Technology | Design Space Search Applying Bayesian Optimization to High-level Design Flow Ryohei Nakayama (UTokyo), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo) ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60 |
Now that circuit scale is increasing, high-level synthesis technology that designs circuits using high-level programming... [more] | ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60 pp.369-374 |
| ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] | 2019-07-24 14:35 |
Kochi | Kochi University of Technology | Design of High Performance Processor for Paillier Algorithm With Homomorphism Chun Cai, Hiromitsu Awano, Makoto Ikeda (Tokyo Univ.) ISEC2019-59 SITE2019-53 BioX2019-51 HWS2019-54 ICSS2019-57 EMM2019-62 |
[more] | ISEC2019-59 SITE2019-53 BioX2019-51 HWS2019-54 ICSS2019-57 EMM2019-62 pp.383-388 |
| HWS, VLD | 2019-02-28 16:20 |
Okinawa | Okinawa Ken Seinen Kaikan | Design of High-Speed Gaussian Sampler Using Micciancio-Walter Algorithm Keitaro Koga (UTokyo), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo) VLD2018-119 HWS2018-82 |
[more] | VLD2018-119 HWS2018-82 pp.157-162 |
| HWS, VLD | 2019-03-01 15:45 |
Okinawa | Okinawa Ken Seinen Kaikan | On Machine Learning Attack Tolerance for PUF-based Device Authentication System Tomoki Iizuka (UTokyo), Yasuhiro Ogasahara, Toshihiro Katashita, Yohei Hori (AIST), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo) VLD2018-133 HWS2018-96 |
Double-Arbiter PUF (DAPUF) and PL-PUF are known to be highly resistant to machine learning attacks. In this paper, we p... [more] |
VLD2018-133 HWS2018-96 pp.237-242 |
| HWS (2nd) |
2018-12-13 16:10 |
Tokyo | Tokyo Univ. Takeda Bldg. Takeda Hall | [Poster Presentation]
Modeling Attacks on Double-Arbiter PUF Using End-to-End Deep Neural Network Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda (UTokyo) |
(Advance abstract in Japanese is available) [more] | |
| HWS (2nd) |
2018-12-13 16:10 |
Tokyo | Tokyo Univ. Takeda Bldg. Takeda Hall | [Poster Presentation]
Base Sampler Design of Micciancio-Walter Algorithm on ASIC Keitaro Koga, Hiromitsu Awano, Makoto Ikeda (UTokyo) |
(Advance abstract in Japanese is available) [more] | |
| HWS (2nd) |
2018-03-03 10:00 |
Okinawa | Hardware Design of Low-Latency ECDSA Signature Generation Shotaro Sugiyama, Hiromitsu Awano, Makoto Ikeda (UTokyo) |
(Advance abstract in Japanese is available) [more] | ||
| HWS (2nd) |
2018-03-03 10:25 |
Okinawa | Implementation of Small-Footprint Co-Processor for Elliptic-Curve Digital-Signature-Algorithm on 256-bit Prime Fields Ryosuke Saito, Hiromitsu Awano, Makoto Ikeda (The Univ. of Tokyo) |
(Advance abstract in Japanese is available) [more] | ||
| HWS (2nd) |
2018-03-03 11:15 |
Okinawa | Evaluation of a 65nm CMOS 12th-extension Prime Field Computation Unit for Optimal Ate Pairing Tadayuki Ichihashi, Hiromitsu Awano, Makoto Ikeda (Univ. Tokyo) |
(Advance abstract in Japanese is available) [more] | ||
| HWS (2nd) |
2018-03-03 11:40 |
Okinawa | Parallel Hardware Implementation of Polynomial Multiplier Based on Number Theoretic Transform Keitaro Koga, Hiromitsu Awano, Makoto Ikeda (UTokyo) |
(Advance abstract in Japanese is available) [more] | ||
| HWS (2nd) |
2018-03-03 13:30 |
Okinawa | Scrambling and Signing during Analog-to-Digital Conversion for Sensing Security Vinod Gadde Vishwa, Makoto Ikeda, Hiromitsu Awano (UTokyo) |
(Advance abstract in Japanese is available) [more] | ||
| VLD, HWS (Joint) |
2018-03-02 14:30 |
Okinawa | Okinawa Seinen Kaikan | Modeling Attacks on Double-Arbiter PUF Using Deep Neural Network Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda (UTokyo) VLD2017-127 |
A deep neural network-based modeling attack for Double-Arbiter PUF (DAPUF) is proposed. Although DAPUF is known to be hi... [more] | VLD2017-127 pp.231-236 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Optimization of Cryptographic Hardware for Optimal Ate Pairing over BN Curves Tadayuki Ichihashi, Hiromitsu Awano, Makoto Ikeda (Tokyo Univ.) VLD2017-30 DC2017-36 |
[more] | VLD2017-30 DC2017-36 pp.19-24 |
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