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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2016-04-14
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Lecture] 1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator
Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Tosinari Watanabe, Hideo Sato, Soshi Sato, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Takaho Tanigawa, Masaaki Niwa, Kenchi Ito, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2016-10
A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array with a high-signal-... [more] ICD2016-10
ICD 2014-04-17
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Lecture] A 1Mb STT-MRAM for Nonvolatile Embedded Memories performing 1.5ns/2.1ns Random Read/Write Cycle Time -- Background Write (BGW) Scheme applied to a 6T2MTJ Memory Cell --
Takashi Ohsawa, Hiroki Koike (Tohoku Univ.), Sadahiko Miura (NEC), Keizo Kinoshita (Tohoku Univ.), Hiroaki Honjo (NEC), Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2014-7
 [more] ICD2014-7
ICD 2014-04-17
Tokyo Kikai-Shinko-Kaikan Bldg. [Panel Discussion] Perspective of emerging memories in systems and systems on emerging memories
Toru Miwa (SanDisk), Koji Nii (Renesas), Shinobu Fujita (Toshiba), Hiroki Koike (Tohoku Univ.), Ken Takeuchi (Chuo Univ.) ICD2014-9
(To be available after the conference date) [more] ICD2014-9
ICD 2014-04-18
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Lecture] A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop
Hiroki Koike (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Sadahiko Miura, Hiroaki Honjo, Tadahiko Sugibayashi (NEC), Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2014-17
We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel jun... [more] ICD2014-17
ICD 2013-04-11
Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Lecture] 1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique -- Achieves 1.0ns/200ps Wake-Up/Power-Off Times --
Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike (Tohoku Univ.), Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome (NEC), Shoji Ikeda, Takahiro Hanyu, Hideo Ohno (Tohoku Univ.) ICD2013-6
A 1Mb embedded memory was designed and fabricated using a cell consisting of four NFETs and two spin-transfer torque mag... [more] ICD2013-6
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