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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 24件中 1~20件目  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, ISEC, SITE, ICSS, EMM, IPSJ-CSEC, IPSJ-SPT [detail] 2018-07-26
14:10
Hokkaido Sapporo Convention Center Compensation of Temperature Induced Flipping-Bits in CMOS SRAM PUF by NMOS Body-Bias
Xuanhao Zhang, Xiang Chen, Hanfeng Sun, Hirofumi Shinohara (Waseda Univ.) ISEC2018-41 SITE2018-33 HWS2018-38 ICSS2018-44 EMM2018-40
PUF suffers from flipping-bits caused by temperature changes which degrade the stability of output. This paper proposes ... [more] ISEC2018-41 SITE2018-33 HWS2018-38 ICSS2018-44 EMM2018-40
pp.333-336
ICD 2018-04-20
13:00
Tokyo   [Invited Talk] Random Circuits for Information Security
Hirofumi Shinohara (Waseda Univ.) ICD2018-11
 [more] ICD2018-11
p.45
SDM, ICD, ITE-IST [detail] 2017-08-01
09:45
Hokkaido Hokkaido-Univ. Multimedia Education Bldg. Parallel Programming of Non-volatile Power-up States of SRAM
Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya (Univ. of Tokyo), Hirofumi Shinohara (Waseda Univ.), Masaharu Kobayashi, Toshiro Hiramoto (Univ. of Tokyo) SDM2017-38 ICD2017-26
A technique for using an ordinary SRAM array for programmable and readable non-volatile (NV) memory is proposed. Paralle... [more] SDM2017-38 ICD2017-26
pp.49-54
ICD, SDM 2014-08-04
09:00
Hokkaido Hokkaido Univ., Multimedia Education Bldg. [Invited Talk] A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology
Koichiro Ishibashi (UEC), Nobuyuki Sugii (LEAP), Kimiyoshi Usami (SIT), Hideharu Amano (KU), Kazutoshi Kobayashi (KIT), Cong-Kha Pham (UEC), Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita (LEAP) SDM2014-62 ICD2014-31
 [more] SDM2014-62 ICD2014-31
pp.1-4
SDM 2014-01-29
14:40
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation
Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii (LEAP), Koichiro Ishibashi (Univ. of Electro- Comm.), Tomoko Mizutani, Toshiro Hiramoto (Univ. of Tokyo), Yasuo Yamaguchi (LEAP) SDM2013-143
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] SDM2013-143
pp.35-38
SDM, ICD 2013-08-02
09:25
Ishikawa Kanazawa University Reduced Cell Current Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells at Supply Voltage of 0.4V
Tomoko Mizutani (Univ. of Tokyo), Yoshiki Yamamoto, Hideki Makiyama, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii (LEAP), Toshiro Hiramoto (Univ. of Tokyo) SDM2013-75 ICD2013-57
Cell current (ICELL) variability in 6T-SRAM composed of silicon-on-thin-BOX (SOTB) MOSFETs by 65nm technology is measure... [more] SDM2013-75 ICD2013-57
pp.47-52
ICD 2013-04-12
14:45
Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Lecture] A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges
Shinichi Moriwaki, Yasue Yamamoto, Toshikazu Suzuki (STARC), Atsushi Kawasumi (Toshiba), Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. Tokyo) ICD2013-20
1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm t... [more] ICD2013-20
pp.103-108
ICD, SDM 2012-08-02
11:25
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido [Invited Talk] Low Energy Dissipation Circuits with 0.5V Operation Voltage and Applications
Hirofumi Shinohara (STARC) SDM2012-67 ICD2012-35
Extremely low voltage operation down to nearly or less than 0.5V has been gathering attention as a fundamental way to re... [more] SDM2012-67 ICD2012-35
pp.23-28
ICD, SDM 2012-08-02
13:00
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido [Invited Lecture] Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power (ULP) Applications
Nobuyuki Sugii, Toshiaki Iwamatsu, Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Hirofumi Shinohara, Hideki Aono, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (LEAP/Renesas), Tomoko Mizutani, Toshiro Hiramoto (IIS, The University of Tokyo) SDM2012-68 ICD2012-36
Needs for low-power CMOS devices are still increasing. Ultralow-voltage-operation (ULV) CMOS with maximum power efficien... [more] SDM2012-68 ICD2012-36
pp.29-32
SDM, ED
(Workshop)
2012-06-29
09:45
Okinawa Okinawa Seinen-kaikan [Invited Talk] Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power (ULP) Applications
Nobuyuki Sugii, Toshiaki Iwamatsu, Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Hirofumi Shinohara, Hideki Aono, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (LEAP/Renesas), Tomoko Mizutani, Toshiro Hiramoto (IIS, Univ. of Tokyo)
Needs for low-power CMOS devices are still increasing. Ultralow-voltage-operation CMOS with maximum power efficiency can... [more]
ICD 2012-04-24
13:50
Iwate Seion-so, Tsunagi Hot Spring (Iwate) 0.4V SRAM with Bit Line Swing Suppression Charge Share Hierarchical Bit Line Scheme
Shinichi Moriwaki, Atsushi Kawasumi (STARC), Toshikazu Suzuki (Panasonic), Yasue Yamamoto, Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) ICD2012-13
 [more] ICD2012-13
pp.67-71
SDM, ICD 2011-08-26
12:55
Toyama Toyama kenminkaikan [Invited Talk] 0.5V Extremely Low Power Circuits for Wireless Sensor Nodes with Energy Harvesting
Makoto Takamiya, Koichi Ishida, Hiroshi Fuketa (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) SDM2011-88 ICD2011-56
0.5V extremely low power circuits for wireless sensor nodes with energy harvesting are shown. Minimum operating voltage ... [more] SDM2011-88 ICD2011-56
pp.87-92
SDM, ICD 2011-08-26
16:30
Toyama Toyama kenminkaikan Energy Efficiency Increase of Integer Unit Enabled by Contention-less Flip-Flops (CLFF) and Separated Supply Voltage between Flip-Flops and Combinational Logics
Hiroshi Fuketa (Univ. of Tokyo), Koji Hirairi (STARC), Tadashi Yasufuku, Makoto Takamiya (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) SDM2011-95 ICD2011-63
 [more] SDM2011-95 ICD2011-63
pp.127-132
ICD 2011-04-19
11:20
Hyogo Kobe University Takigawa Memorial Hall 0.5-V, 5.5-nsec Access Time, Bulk-CMOS 8T SRAM with Suspended Bit-Line Read Scheme
Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara (STARC) ICD2011-12
A low-voltage high-speed bulk-CMOS 8T SRAM is proposed. A novel 8-transistor (8T) memory cell with a complementary read ... [more] ICD2011-12
pp.65-70
ICD 2010-04-22
10:50
Kanagawa Shonan Institute of Tech. A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Yasunobu Nakase, Hirofumi Shinohara (Renesas Electronics) ICD2010-3
We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. ... [more] ICD2010-3
pp.13-16
ICD 2008-12-12
16:35
Tokyo Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan Post-Silicon Programmed Body-Biasing Platform Suppressing Device Variability in 45 nm CMOS Technology
Issei Kashima, Hiroaki Suzuki, Masanori Kurimoto (Renesas Technology Corp), Tadao Yamanaka (Renesas Design), Hidehiro Takata (Renesas Technology Corp), Hiroshi Makino (Osaka Institute of Tech), Hirofumi Shinohara (Renesas Technology Corp) ICD2008-128
The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technolog... [more] ICD2008-128
pp.137-142
SDM [detail] 2008-11-14
13:50
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] [Invited]Robust Design of Embedded SRAM on Deep-submicron Technology
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Hirofumi Shinohara (Renesas Technology Corp.) SDM2008-178
We develop high-density SRAM module in deep-submicron CMOS technology with the variation tolerant assist circuits agains... [more] SDM2008-178
pp.55-60
VLD 2008-09-29
13:30
Ishikawa   [Invited Talk] Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold Driven Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling
Masanori Kurimoto, Hiroaki Suzuki (Renesas Technology), Rei Akiyama, Tadao Yamanaka, Haruyuki Okuma (Renesas Design), Hidehiro Takata, Hirofumi Shinohara (Renesas Technology) VLD2008-47
 [more] VLD2008-47
pp.1-6
ICD, SDM 2008-07-17
10:30
Tokyo Kikai-Shinko-Kaikan Bldg. A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka (Renesas Tech.), Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Katsuji Satomi, Hironori Akamatsu (Matsushita Elec.), Hirofumi Shinohara (Renesas Tech.) SDM2008-131 ICD2008-41
We develop 512 Kb SRAM module in 45 nm LSTP CMOS technology with the variation tolerant assist circuits against process ... [more] SDM2008-131 ICD2008-41
pp.17-22
ICD, SDM 2007-08-24
16:05
Hokkaido Kitami Institute of Technology A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues
Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial) SDM2007-168 ICD2007-96
We propose a new 2port SRAM with a 8T single-read-bitline (SRBL) memory cell for 45nm SOCs. Access time tends to be slow... [more] SDM2007-168 ICD2007-96
pp.145-148
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