IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 26  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
WIT 2021-06-01
13:50
Online Online Investigation into muscle activities when swallowing by using machine learning
Atsuo Taniguchi, Hiroaki Yoshida (Shinshu Univ.), Nobuyuki Ohmori (Nagano Pref. General Industrial Technology Center), Yoshito Koyama, Hiroshi Kurita (Shinshu Univ.) WIT2021-6
Japan faces the serious concerns of aging and aspiration (accidental swallowing) is one of the big problems to be solved... [more] WIT2021-6
pp.28-31
WIT 2018-08-09
15:55
Nagano   Comparision between healthy subjects and disability subjects while swallowing by using surface electromyography
Toru Nagasaka, Hiroaki Yoshida, Masayoshi Kamijo (Shinshu Univ), Nobuyuki Omori (Nagano Prefecture General Industrial Technology Center), Hideya Momose (Nishizawa Electric Meters Manufacturing Co.,Ltd) WIT2018-16
(To be available after the conference date) [more] WIT2018-16
pp.19-20
WIT, ASJ-H 2017-02-10
14:30
Ehime Ehime Univ. The measurement of swallowing by using electromyography electrodes attached to a sheet for food evaluation
Nobuyuki Ohmori, Chihiro Murasawa, Jumpei Aizawa (Nagano Prefecture General Industrial Technology Center), Hideya Momose (Nishizawa Electric Meters Manufacturing), Yoshito Koyama, Hiroshi Kurita, Hiroaki Yoshida, Masayoshi Kamijo (Shinshu Univ.) WIT2016-65
(To be available after the conference date) [more] WIT2016-65
pp.13-18
WIT, ASJ-H 2015-02-14
10:45
Ehime Ehime University, Johoku Campus The measurement of swallowing by using electromyography electrodes attached to a sheet for food evaluation
Nobuyuki Ohmori, Chihiro Murasawa, Jumpei Aizawa (NGITC), Yoshito Koyama, Hiroshi Kurita, Hiroaki Yoshida, Masayoshi Kamijo (Shinshu Univ.) WIT2014-83
 [more] WIT2014-83
pp.53-58
VLD, IPSJ-SLDM 2013-05-16
16:25
Fukuoka Kitakyushu International Conference Center SoC System Design Methodology with Fully-Coherent Cache
Kodai Moritaka (NAIST), Hiroaki Yoshida, Mitsuru Tomono (FLA), Yasuhiko Nakashima (NAIST) VLD2013-10
As Chip Multi-Processors (CMPs) includes more processor cores in a single chip, the impact of its memory model on the en... [more] VLD2013-10
pp.73-78
IBISML 2013-03-05
11:25
Aichi Nagoya Institute of Technology Elimination of redundant features by Kernel Methods and Random Matrix Theory
Hideko Kawakubo, Hiroaki Yoshida (Ochanomizu Univ) IBISML2012-102
Feature selection can be used to detect factors that affect a certain phenomenon. If the subset of the selected factors ... [more] IBISML2012-102
pp.69-76
LQE 2012-12-13
11:25
Tokyo Kikai-Shinko-Kaikan Bldg. 1550nm/1310nm dual wavelength high power LD
Shintaro Morimoto, Hiroshi Mori, Atsushi Yamada, Yasuaki Nagashima, Motoaki Fujita, Shinichi Onuki, Hiroaki Yoshidaya, Kazuaki Mise (Anritsu Devices) LQE2012-125
We have developed a high power 1550nm/1310nm dual wavelength laser diode, which is suitable for Optical Time Domain Refl... [more] LQE2012-125
pp.19-22
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-26
11:20
Fukuoka Centennial Hall Kyushu University School of Medicine Partially-Programmable Circuits with CAMs
Atsushi Matsuo, Shigeru Yamashita (Ritsumeikan Univ.), Hiroaki Yoshida (Fujitsu Laboratories of Amerika) VLD2012-64 DC2012-30
This paper proposes a new framework for the ECO after the manufacturing. More precisely, we propose a circuit model wher... [more] VLD2012-64 DC2012-30
pp.31-36
VLD 2012-03-06
15:05
Oita B-con Plaza High-Level Synthesis for Mixed Behavioral-Level/RTL Design Descriptions
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2011-128
It is widely known that high-level synthesis technology can improve the design productivity dramatically by raising the ... [more] VLD2011-128
pp.49-54
EE, IEE-SPC 2011-07-29
13:45
Hokkaido   Development of High Performance Large-sized Lithium-ion Cells for Space Application
Makoto Kawase, Hitoshi Naito (JAXA), Hiroaki Yoshida, Masazumi Segawa (GYT) EE2011-15
The specific advantages of lithium-ion battery in energy density and working voltage offer the possibility of huge reduc... [more] EE2011-15
pp.97-100
CQ, CS
(Joint)
2011-04-21
13:40
Kagoshima Yakushima Environmental Culture Village Center [Special Talk] Standardization Trend of Optical Access in IEEE -- IEEE P1904.1 SIEPON Overview --
Motoyuki Takizawa, Hiroaki Yoshida (Fujitsu Telecom) CS2011-1 CQ2011-6
In the optical access area, GE-PON, which was developed in IEEE 802.3 WG, has been prevailing especially in Asian countr... [more] CS2011-1 CQ2011-6
pp.1-6(CS), pp.29-34(CQ)
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-29
13:50
Fukuoka Kyushu University Rapid SoC Prototyping Based on Virtual Multi-Processor Model
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) VLD2010-58 DC2010-25
To meet both high performance and high energy efficiency, System-on-Chip (SoC) has a heterogenous architec- ture includi... [more] VLD2010-58 DC2010-25
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-29
14:10
Fukuoka Kyushu University A Scalable Heuristic for Incremental High-Level Synthesis
Shohei Ono (Univ. Tokyo), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) VLD2010-59 DC2010-26
Recently, high-level synthesis techniques have been widely used to achieve
high design productivity by enabling a desig... [more]
VLD2010-59 DC2010-26
pp.13-18
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-30
11:05
Fukuoka Kyushu University Evaluation of FPGA Implementation Techniques for High-Performance SoC Prototypes
Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) VLD2010-68 DC2010-35
With the increasing scale and shrinking time-to-market of SoC systems, prototype implementations of SoCs on FPGAs are co... [more] VLD2010-68 DC2010-35
pp.79-84
VLD 2010-03-11
11:15
Okinawa   High-Level Synthesis of Programmable Hardware Accelerators Considering Potential Varieties
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) VLD2009-110
Recently, programmable hardware accelerators have attracted more attention as an enabling solution for post-silicon engi... [more] VLD2009-110
pp.67-72
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-04
10:20
Kochi Kochi City Culture-Plaza Increasing Yield Using Partially-Programmable Circuits
Shigeru Yamashita (Ritsumeikan Univ.), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2009-59 DC2009-46
This paper proposes to use Partially-Programmable Circuits (PPCs) which are obtained from conventional logic circuits by... [more] VLD2009-59 DC2009-46
pp.125-130
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-04
15:20
Kochi Kochi City Culture-Plaza Automatic Generation of Design-Specific Cell Libraries
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) VLD2009-67 DC2009-54
In spite of the significant advances of computer-aided design tools for LSIs over the decades, there has been a large pe... [more] VLD2009-67 DC2009-54
pp.179-184
VLD 2009-03-12
10:30
Okinawa   A Formal Verification Method for On-Chip Programmable Interconnect
Takaaki Tagawa, Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) VLD2008-142
As the development cost increases, programmable devices such as FPGAs are becoming critically important. A key componen... [more] VLD2008-142
pp.95-100
VLD 2009-03-12
14:15
Okinawa   Automatic generation of Network-on-Chip topology under link length and latency constraint
Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida (Univ. of Tokyo/JST-CREST), Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (Univ. of Tokyo/JST-CREST) VLD2008-148
With wire delay becoming dominant compared to transistor delay in deep-submicron era, the performance of SoC is more aff... [more] VLD2008-148
pp.129-134
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-18
13:00
Fukuoka Kitakyushu Science and Research Park Improving the Accuracy of Rule-based Equivalence Checking of High-level Desciptions by Identifying Potential Internal Equivalences
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo)
Rule-based equivalence checking of high-level design descriptions proves the equivalence of two high-level design descri... [more] VLD2008-78 DC2008-46
pp.109-114
 Results 1 - 20 of 26  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan