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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2015-03-07
14:15		 Kagoshima   Speed Up co-Simulation for Verification of Embedded Systems
Hiroaki Nakata, Kenta Morishima, Yasuo Sugure (Hitachi) CPSY2014-183 DC2014-109		 In order to apply co-simulation method to verification of many embedded systems, we speeded up co-simulation between a m... [more] CPSY2014-183 DC2014-109
pp.137-142
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
16:30		 Osaka Shoushin Kaikan A Low-Power Full-HD H.264 High-Profile Codec Based on a Heterogeneous Multiprocessor Architecture
Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda (Renesas Tech Corp.), Koji Hosogi, Hiroaki Nakata, Masakazu Ehama (Hitachi Ltd.), Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe (Renesas Tech Corp.) ICD2008-148		 A video-size-scalable H.264 High-Profile codec including 19 application-specific CPUs for extensibility to multiple stan... [more] ICD2008-148
pp.111-116
SIP, ICD, IE, IPSJ-SLDM
(Joint) [detail]		 2007-10-26
09:00		 Fukushima Aidu-Higasiyama-Onsen Kuturogijuku Performance Evaluation of Variable Length Encoder/Decoder Hardware
Takafumi Yuasa, Hiroaki Nakata (Hitachi, Ltd.), Kazushi Akie, Fumitaka Izuhara, Kenichi Iwata (Renesas Technology Corp.) SIP2007-123 ICD2007-112 IE2007-82		 We developed Variable Length Encoder/Decoder hardware for multi-codecs. Our hardware processes VLC(Variable Length Code)... [more] SIP2007-123 ICD2007-112 IE2007-82
pp.1-5
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