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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2022-01-31 13:45 |
Online | Online | [Invited Talk]
Single-digit-nanometer magnetic tunnel junction technology for high-capacity STT-MRAM Butsurin Jinnai, Junta Igarashi, Takanobu Shinoda, Kyota Watanabe, Takuya Funatsu, Hideo Sato, Shunsuke Fukami, Hideo Ohno (Tohoku Univ.)  SDM2021-69 |
[more] | SDM2021-69 pp.5-8 |
| MRIS, ITE-MMS | 2017-10-19 13:45 |
Niigata | Kashiwazaki energy hall, Niigata | [Invited Talk]
Analog spintronics devices and its application to artificial neural networks Hisanao Akima, William Borders, Shunsuke Fukami, Satoshi Moriya, Shouta Kurihara, Aleksandr Kurenkov, Yoshihiko Horio, Shigeo Sato, Hideo Ohno (Tohoku Univ.) MR2017-18 |
Developing dedicated integrated circuits operating with low power consumption is indispensable to realize a large scale ... [more] | MR2017-18 pp.7-12 |
| MBE, NC (Joint) |
2017-03-13 14:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Autoassociative Memory System Using Analogue Magnetic Memory Device Shouta Kurihara, Hisanao Akima, William A. Borders, Shunsuke Fukami, Satoshi Moriya, Aleksandr Kurenkov, Ryota Shimohashi, Yoshihiko Horio, Shigeo Sato, Hideo Ohno (Tohoku Univ.) NC2016-85 |
[more] | NC2016-85 pp.127-132 |
| ICD, SDM, ITE-IST [detail] | 2016-08-03 11:25 |
Osaka | Central Electric Club | [Invited Talk]
A Three-Terminal Spin-Orbit Torque Switching Magnetic Memory Device
-- Toward Realization of High-Speed and Low-Power Nonvolatile Integrated Circuits -- Shunsuke Fukami, Tetsuro Anekawa, Ayato Ohkawara, Chaoliang Zhang, Hideo Ohno (Tohoku Univ.) SDM2016-63 ICD2016-31 |
Integrated circuits with non-volatile spintronics memory devices open up new pathways toward ultralow-power and high-per... [more] | SDM2016-63 ICD2016-31 pp.99-103 |
| ICD | 2016-04-14 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Tosinari Watanabe, Hideo Sato, Soshi Sato, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Takaho Tanigawa, Masaaki Niwa, Kenchi Ito, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2016-10 |
A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array with a high-signal-... [more] | ICD2016-10 pp.51-56 |
| ICD | 2015-04-17 13:55 |
Nagano | [Tutorial Lecture]
Nonvolatile Logic-in-Memory Architecture and Its Applications to Low-Power VLSI System Takahiro Hanyu, Daisuke Suzuki, Akira Mochizuki, Masanori Natsui, Naoya Onizawa (Tohoku Univ.), Tadahiko Sugibayashi (NEC), Shoji Ikeda, Tetsuo Endoh, Hideo Ohno (Tohoku Univ.) ICD2015-12 |
[more] | ICD2015-12 pp.57-61 |
|
| ICD, SDM | 2014-08-04 14:55 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
A 90-nm Three-terminal MRAM Embedded Nonvolatile Microcontroller for Standby-Power-Critical Applications Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara (NEC), Keizo Kinoshita, Shunsuke Fukami (Tohoku Univ.), Sadahiko Miura (NEC), Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.), Tadahiko Sugibayashi (NEC) SDM2014-69 ICD2014-38 |
[more] | SDM2014-69 ICD2014-38 pp.39-44 |
| ICD | 2014-04-17 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A 1Mb STT-MRAM for Nonvolatile Embedded Memories performing 1.5ns/2.1ns Random Read/Write Cycle Time
-- Background Write (BGW) Scheme applied to a 6T2MTJ Memory Cell -- Takashi Ohsawa, Hiroki Koike (Tohoku Univ.), Sadahiko Miura (NEC), Keizo Kinoshita (Tohoku Univ.), Hiroaki Honjo (NEC), Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2014-7 |
[more] | ICD2014-7 pp.33-38 |
| ICD | 2014-04-17 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine Shoun Matsunaga (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi (NEC), Masanori Natsui, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2014-8 |
We demonstrate a 1-Mb nonvolatile TCAM-based search engine using 90-nm CMOS and perpendicular MTJ technologies for an ul... [more] | ICD2014-8 pp.39-44 |
| ICD | 2014-04-18 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop Hiroki Koike (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Sadahiko Miura, Hiroaki Honjo, Tadahiko Sugibayashi (NEC), Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2014-17 |
We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel jun... [more] | ICD2014-17 pp.85-90 |
| ICD | 2013-04-11 14:20 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique
-- Achieves 1.0ns/200ps Wake-Up/Power-Off Times -- Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike (Tohoku Univ.), Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome (NEC), Shoji Ikeda, Takahiro Hanyu, Hideo Ohno (Tohoku Univ.) ICD2013-6 |
A 1Mb embedded memory was designed and fabricated using a cell consisting of four NFETs and two spin-transfer torque mag... [more] | ICD2013-6 pp.27-32 |
| ICD | 2013-04-11 14:45 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
Fabrication of a Nonvolatile TCAM Chip Based on 4T-2MTJ Cell Structure Shoun Matsunaga (Tohoku Univ.), Sadahiko Miura, Hiroaki Honjo (NEC), Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2013-7 |
Higher density and lower standby power are demanded in ternary content-addressable memory (TCAM), that realizes huge num... [more] | ICD2013-7 pp.33-38 |
| ICD | 2013-04-11 16:20 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | Highly Reliable Logic Primitive Gates for Spintronics-Based Logic LSI Yukihide Tsuji, Ryusuke Nebashi, Noboru Sakimura, Ayuka Morioka, Hiroaki Honjo, Keiichi Tokutome, Sadahiko Miura (NEC), Tetsuhiro Suzuki (Renesas Electronics Corp.), Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno (Tohoku Univ.), Tadahiko Sugibayashi (NEC) ICD2013-9 |
Implementing redundancy within a Spintronis Primitive Gata (SPG) using multi-terminal DWM cells ensures high reliability... [more] | ICD2013-9 pp.41-46 |
| ICD | 2012-04-24 10:50 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | A Non-Volatile Content Addressable Memory Using Three-Terminal Magnetic Domain Wall Motion Cells Ryusuke Nebashi, Noboru Sakimura, Yukihide Tsuji (NEC), Shunsuke Fukami (Tohoku Univ.), Hiroaki Honjo, Shinsaku Saito, Sadahiko Miura, Nobuyuki Ishiwata (NEC), Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno (Tohoku Univ.), Tadahiko Sugibayashi (NEC) ICD2012-10 |
A 5-ns search operation of a non-volatile content addressable memory was demonstrated. The CAM macro, with a capacity of... [more] | ICD2012-10 pp.49-54 |
| ICD | 2011-04-18 10:00 |
Hyogo | Kobe University Takigawa Memorial Hall | [Invited Talk]
Trends and Multi-level-cell Technology of Spin Transfer Torque Memory Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.) ICD2011-1 |
A MLC (Multi-level cell) SPRAM (Spin transfer torque RAM) with series-stacked MTJs (Magnetic tunnel junctions) was devel... [more] | ICD2011-1 pp.1-5 |
| SDM | 2010-11-11 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Trends of Magnetic Memory; Multi-Level-Cell Spin Transfer Torque Memory Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.) SDM2010-173 |
A MLC (Multi-level cell) SPRAM (Spin transfer torque RAM) with series-stacked MTJs (Magneto tunnel junctions) was develo... [more] | SDM2010-173 pp.11-15 |
| ICD | 2010-04-22 15:20 |
Kanagawa | Shonan Institute of Tech. | Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array Daisuke Suzuki, Masanori Natsui, Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa (ARL, Hitachi, Ltd.), Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2010-9 |
This paper presents a nonvolatile LUT (Lookup-Table) circuit in FPGA (Field-Programmable Gate Array) using a MTJ (Magnet... [more] | ICD2010-9 pp.47-52 |
| ICD | 2010-04-22 15:45 |
Kanagawa | Shonan Institute of Tech. | A 32-Mb SPRAM with localized bi-directional write driver, '1'/'0' dual-array equalized reference scheme, and 2T1R memory cell layout Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi (Hitachi), Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.) ICD2010-10 |
A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ... [more] | ICD2010-10 pp.53-57 |
| ITE-MMS, MRIS | 2009-10-08 13:55 |
Fukuoka | FUKUOKA traffic center | [Invited Talk]
Nonvolatile RAM using spin transfer torque magnetization reversal (SPRAM) Hiromasa Takahashi, Kenchi Ito, Jun Hayakawa, Katsuya Miura, Hiroyuki Yamamoto, Michihiko Yamanouchi (ARL, Hitachi, Ltd.), Kazuo Ono, Riichiro Takemura, Takayuki Kawahara (CRL, Hitachi, Ltd.), Ryutaro Sasaki (RIEC Tohoku Univ.), Haruhiro Hasegawa (RIEC Tohoku Univ., ARL, Hitachi, Ltd.), Shoji Ikeda (RIEC Tohoku Univ.), Hideyuki Matsuoka (ARL, Hitachi, Ltd.), Hideo Ohno (RIEC Tohoku Univ.) |
The SPRAM (Spin Transfer Torque MRAM) is one of nonvolatile memories that “writing” is done by that a magnetization in M... [more] | |
| SDM, ED | 2009-06-24 14:30 |
Overseas | Haeundae Grand Hotel, Busan, Korea | [Invited Talk]
Advanced magnetic tunnel junctions for hybrid spintronics/CMOS circuits Shoji Ikeda (Tohoku Univ.), Jun Hayakawa (Hitachi, Ltd.), Huadong Gan, Kotaro Mizumuma, Ji Ho Park (Tohoku Univ.), Hiroyuki Yamamoto, Katsuya Miura (Hitachi, Ltd./Tohoku Univ.), Haruhiro Hasegawa, Ryutaro Sasaki, Toshiyasu Meguro (Tohoku Univ.), Kenchi Ito (Hitachi, Ltd.), Fumihiro Matsukura, Hideo Ohno (Tohoku Univ.) ED2009-51 SDM2009-46 |
Magnetoresistive random access memory (MRAM) using magnetic tunnel junctions (MTJs) is one of the candidates of universa... [more] | ED2009-51 SDM2009-46 pp.5-8 |
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