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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 36  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
16:15
Online Online A Generation Method of Easily Testable Functional Time Expansion Models Using Testability Measure Based on Data Amount
Kenta Nakamura, Toshinori Hosokawa, Yuta Ishiyama (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) CPSY2020-13 DC2020-13
 [more] CPSY2020-13 DC2020-13
pp.81-86
DC 2018-02-20
11:40
Tokyo Kikai-Shinko-Kaikan Bldg. A test generation method based on k-cycle testing for finite state machines
Yuya Kinoshita, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2017-81
Recent advances in semiconductor technologies have resulted in VLSI circuit density and complexity. As a result, efficie... [more] DC2017-81
pp.25-30
DC 2017-02-21
15:05
Tokyo Kikai-Shinko-Kaikan Bldg. A Method of Strongly Secure Scan Design Using Extended Shift Registers
Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2016-80
 [more] DC2016-80
pp.35-40
DC 2016-06-20
15:15
Tokyo Kikai-Shinko-Kaikan Bldg. A Binding Method for Testability to Generate Easily Testable Functional Time Expansion Models
Mamoru Sato, Toshinori hosokawa, Tetsuya Masuda, Jun Nishimaki (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2016-14
A test generation method for datapaths using easily testable functional time expansion models was proposed as efficient ... [more] DC2016-14
pp.25-30
DC 2015-02-13
14:55
Tokyo Kikai-Shinko-Kaikan Bldg A Method of Scheduling in High-Level Synthesis for Hierarchical Testability
Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-84
We previously proposed a binding method for hierarchical testability to increase the number of hierarchically testable f... [more] DC2014-84
pp.37-42
DC 2014-06-20
16:00
Tokyo Kikai-Shinko-Kaikan Bldg. A Binding Method for Hierarchical Testability Using Results of Test Environment Generation
Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-16
Hierarchical test generation methods using functional register-transfer level circuits have been proposed as efficient t... [more] DC2014-16
pp.39-44
DC 2014-06-20
16:25
Tokyo Kikai-Shinko-Kaikan Bldg. An evaluation for Testability of Functional k-Time Expansion Models
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-17
A test generation method using functional k-time expansion models for data paths was proposed. In the test generation
m... [more]
DC2014-17
pp.45-50
DC 2013-06-21
13:45
Tokyo Kikai-Shinko-Kaikan Bldg. A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits
Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10
In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design pro... [more] DC2013-10
pp.1-6
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-28
09:50
Miyazaki NewWelCity Miyazaki On Secure and Testable Scan Design Utilizing Shift Register Quasi-Equivalents
Katsuya Fujiwara (Akita Univ.), Hideo Fujiwara (Osaka Gakuin Univ.), Hideo Tamamoto (Akita Univ.) VLD2011-54 DC2011-30
 [more] VLD2011-54 DC2011-30
pp.13-18
DC 2011-02-14
11:50
Tokyo Kikai-Shinko-Kaikan Bldg. A Pattern Generation Method to Uniform Initial Temperature of Test Application
Emiko Kosoegawa, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-63
Circuit failure prediction is essential to ensure product quality and in-field reliability. The basic principle of circu... [more] DC2010-63
pp.27-32
DC 2011-02-14
13:45
Tokyo Kikai-Shinko-Kaikan Bldg. Test Pattern Generation for Highly Accurate Delay Testing
Keigo Hori (NAIST), Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-64
We propose a new faster-than-at-speed test method to detect small delay defects. As semiconductor technology is scaling ... [more] DC2010-64
pp.33-38
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-12-01
09:10
Fukuoka Kyushu University SREEP: A Tool for Secure Scan Design Using Shift Register Equivalents
Katsuya Fujiwara (Akita Univ.), Hideo Fujiwara (NAIST), Hideo Tamamoto (Akita Univ.) VLD2010-72 DC2010-39
 [more] VLD2010-72 DC2010-39
pp.107-112
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-12-01
11:25
Fukuoka Kyushu University A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description
Ryoichi Inoue, Hiroaki Fujiwara, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) VLD2010-76 DC2010-43
Although many works on test generation algorithms for sequential circuits have been reported so far, it is still very ha... [more] VLD2010-76 DC2010-43
pp.143-148
ICD
(Workshop)
2010-08-16
- 2010-08-18
Overseas Ho Chi Minh City University of Technology [Invited Talk] Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism
Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.)
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are takin... [more]
DC 2010-06-25
13:30
Tokyo Kikai-Shinko-Kaikan Bldg. A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths
Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2010-8
Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g.\ the clock skew, higher throughput... [more] DC2010-8
pp.1-6
CAS, MSS, VLD, SIP 2010-06-21
11:15
Hokkaido Kitami Institute of Technology Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure Scan Design
Katsuya Fujiwara (Akita Univ.), Hideo Fujiwara (NAIST), Hideo Tamamoto (Akita Univ.) CAS2010-6 VLD2010-16 SIP2010-27 CST2010-6
 [more] CAS2010-6 VLD2010-16 SIP2010-27 CST2010-6
pp.31-36
DC 2010-02-15
09:25
Tokyo Kikai-Shinko-Kaikan Bldg. Test Pattern Re-Ordering for Thermal-Uniformity during Test
Makoto Nakao, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-66
Power consumption during VLSI testing varies spatially and temporally, and it leads to temperature variation during tes... [more] DC2009-66
pp.7-12
DC 2010-02-15
14:35
Tokyo Kikai-Shinko-Kaikan Bldg. Seed Selection for High Quality Delay Fault Test in BIST
Akira Taketani, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-74
In this paper, we target a scan BIST architecture that consists of LFSR, phase shifter and MISR, and propose a method to... [more] DC2009-74
pp.57-62
DC 2009-12-11
13:50
Shimane   Enumeration and Synthesis of Shift Register Equivalents for Secure Scan Design
Katsuya Fujiwara (Akita Univ.), Hideo Fujiwara (NAIST), Hideo Tamamoto (Akita Univ.) DC2009-58
(To be available after the conference date) [more] DC2009-58
pp.13-18
DC 2009-02-16
15:45
Tokyo   Resource Binding to Minimize the Number of RTL Paths
Yuichi Uemoto, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Scie and Tech.) DC2008-77
Though path delay testing is promising to detect small delay in a VLSI circuit, it has a practical problem that the numb... [more] DC2008-77
pp.55-60
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