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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
09:35		 Kanagawa   A Design Method of Network-on-Chip Architecture for FPGA
Hideki Katabami, Hiroshi Saito (Aizu Univ.) VLD2012-108 CPSY2012-57 RECONF2012-62		 This paper proposes a design method for a Globally-Asynchronous Locally-Synchronous Network-on-Chip (GALS-NoC) on Altera... [more] VLD2012-108 CPSY2012-57 RECONF2012-62
pp.7-12
VLD 2011-09-27
10:10		 Fukushima University of Aizu A Design Method of Network-on-Chip Architecture for FPGA
Hideki Katabami, Hiroshi Saito (Aizu Univ.) VLD2011-48		  [more] VLD2011-48
pp.43-48
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