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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 18 of 18  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2016-04-14
Tokyo Kikai-Shinko-Kaikan Bldg. A 64kb 16nm Asynchronous Disturb Current Free 2-Port SRAM with PMOS Pass-Gates for FinFET Technologies
Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Koo-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chin-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang (TSMC) ICD2016-4
 [more] ICD2016-4
ICD 2014-01-28
Kyoto Kyoto Univ. Tokeidai Kinenkan [Poster Presentation] An Autonomous Control Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory
Yuta Kimi, Yohei Nakata, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa (Kobe Univ.), Makoto Nagata (Kobe Univ./JST CREST), Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai (Renesas Electronics Corporation), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST CREST) ICD2013-125
Processor reliability is getting more critical issue since technology scaling degrades processor tolerance against power... [more] ICD2013-125
SDM, ICD 2013-08-02
Ishikawa Kanazawa University A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii (Renesas Electronics), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) SDM2013-76 ICD2013-58
 [more] SDM2013-76 ICD2013-58
ICD 2012-12-18
Tokyo Tokyo Tech Front A Stable Chip-ID Generating Physical Uncloneable Function Using Random Address Errors in SRAM
Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii (Renesas) ICD2012-114
 [more] ICD2012-114
ICD 2012-04-24
Iwate Seion-so, Tsunagi Hot Spring (Iwate) [Invited Talk] Write-/Read- Disturb Issues and Circuit Solutions
Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki (Renesas Electronics) ICD2012-11
This paper describes some circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage agai... [more] ICD2012-11
ICD 2012-04-24
Iwate Seion-so, Tsunagi Hot Spring (Iwate) A Chip-ID Generating Circuit for Dependable LSI using Random Address Errors on Embedded SRAM and On-Chip Memory BIST
Hidehiro Fujiwara, Makoto Yabuuchi, Hirofumi Nakano, Hiroyuki Kawai, Koji Nii, Kazutami Arimoto (Renesas Electronics) ICD2012-17
 [more] ICD2012-17
SDM, ICD 2011-08-26
Toyama Toyama kenminkaikan Dependable SRAM with Enhanced Read-/Write-Margins by Fine-Grained Assist Bias Control for Low-Voltage Operation
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto (Renesas) SDM2011-91 ICD2011-59
 [more] SDM2011-91 ICD2011-59
SDM, ICD 2011-08-26
Toyama Toyama kenminkaikan A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue
Yuichiro Ishii, Hidehiro Fujiwara, Koji Nii (Renesas Electronics), Hideo Chigasaki, Osamu Kuromiya, Tsukasa Saiki (Renesas Design), Atsushi Miyanishi, Yuji Kihara (Renesas Electronics) SDM2011-92 ICD2011-60
We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vddmin). Active bi... [more] SDM2011-92 ICD2011-60
SDM, ICD 2011-08-26
Toyama Toyama kenminkaikan A Dynamic body-biased SRAM with Asymmetric Halo Implant MOSFETs
Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Koji Maekawa, Motoshige Igarashi, Koji Nii (Renesas) SDM2011-93 ICD2011-61
In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design ... [more] SDM2011-93 ICD2011-61
ICD 2009-04-14
Miyagi Daikanso (Matsushima, Miyagi) A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme
Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2009-6
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster a... [more] ICD2009-6
ICD 2009-04-14
Miyagi Daikanso (Matsushima, Miyagi) A 7T/14T Dependable SRAM and Its Array Structure to Avoid Half Selection
Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST-CREST) ICD2009-7
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. The dep... [more] ICD2009-7
ICD 2008-12-12
Tokyo Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control
Kosuke Yamaguchi, Hidehiro Fujiwara, Takashi Takeuchi, Yu Otake, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kove Univ) ICD2008-127
We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-... [more] ICD2008-127
VLD, IPSJ-SLDM 2008-05-09
Hyogo Kobe Univ. A Dependable SRAM with high-reliability mode and high-speed mode.
Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, “quality of a bit (QoB)” for i... [more] VLD2008-12
ICD, SDM 2007-08-24
Hokkaido Kitami Institute of Technology An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2007-167 ICD2007-95
This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM... [more] SDM2007-167 ICD2007-95
ICD, ITE-IST 2007-07-26
Hyogo   Cross-Layer Design for Low-Power Wireless Sensor Node using Long-Wave Standard Time Code
Yu Otake, Masumi Ichien, Takashi Takeuchi, Akihiro Gion, Shinji Mikami, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto (Kobe Univ.) ICD2007-49
We propose Isochronous-MAC (I-MAC) using the Long-Wave Standard Time Code, and introduce cross-layer design for a low-po... [more] ICD2007-49
ICD, ITE-IST 2007-07-26
Hyogo   A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing
Shunsuke Okumura, Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-53
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten tran... [more] ICD2007-53
ICD 2007-04-12
Oita   A Novel Two-Port SRAM for Low Bitline Power Using Majority Logic and Data-Bit Reordering
Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-7
 [more] ICD2007-7
ICD, SDM 2006-08-18
Hokkaido Hokkaido University A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment
Hiroki Noguchi (Kobe Univ.), Yasuhiro Morita (Kanazawa Univ.), Hidehiro Fujiwara, Kentaro Kawakami, Junichi Miyakoshi (Kobe Univ.), Shinji Mikami (Kanazawa Univ.), Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
 [more] SDM2006-152 ICD2006-106
 Results 1 - 18 of 18  /   
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