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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2024-04-11 10:20 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
A 3nm 32.5 TOPS/W, 55.0 TOPS/mm2 and 3.78 Mb/mm2 Fully Digital Computing-in-Memory Supporting INT12 x INT12 with Parallel MAC Architecture HIdehiro Fujiwara (TSMC) |
[more] | |
| ICD | 2024-04-12 15:20 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang (TSMC) |
[more] | |
| ICD | 2023-04-11 09:55 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Talk]
A 4-nm 6163-TOPS/W/b 4790-TOPS/mm2/b SRAM based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang (TSMC) |
[more] | |
| ICD | 2016-04-14 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A 64kb 16nm Asynchronous Disturb Current Free 2-Port SRAM with PMOS Pass-Gates for FinFET Technologies Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Koo-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chin-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang (TSMC)  ICD2016-4 |
[more] | ICD2016-4 pp.17-20 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
An Autonomous Control Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory Yuta Kimi, Yohei Nakata, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa (Kobe Univ.), Makoto Nagata (Kobe Univ./JST CREST), Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai (Renesas Electronics Corporation), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST CREST) ICD2013-125 |
Processor reliability is getting more critical issue since technology scaling degrades processor tolerance against power... [more] | ICD2013-125 p.59 |
| SDM, ICD | 2013-08-02 09:50 |
Ishikawa | Kanazawa University | A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii (Renesas Electronics), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) SDM2013-76 ICD2013-58 |
[more] | SDM2013-76 ICD2013-58 pp.53-57 |
| ICD | 2012-12-18 09:55 |
Tokyo | Tokyo Tech Front | A Stable Chip-ID Generating Physical Uncloneable Function Using Random Address Errors in SRAM Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii (Renesas) ICD2012-114 |
[more] | ICD2012-114 pp.91-95 |
| ICD | 2012-04-24 11:15 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | [Invited Talk]
Write-/Read- Disturb Issues and Circuit Solutions Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki (Renesas Electronics) ICD2012-11 |
This paper describes some circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage agai... [more] | ICD2012-11 pp.55-60 |
| ICD | 2012-04-24 15:40 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | A Chip-ID Generating Circuit for Dependable LSI using Random Address Errors on Embedded SRAM and On-Chip Memory BIST Hidehiro Fujiwara, Makoto Yabuuchi, Hirofumi Nakano, Hiroyuki Kawai, Koji Nii, Kazutami Arimoto (Renesas Electronics) ICD2012-17 |
[more] | ICD2012-17 pp.91-95 |
| SDM, ICD | 2011-08-26 14:40 |
Toyama | Toyama kenminkaikan | Dependable SRAM with Enhanced Read-/Write-Margins by Fine-Grained Assist Bias Control for Low-Voltage Operation Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto (Renesas) SDM2011-91 ICD2011-59 |
[more] | SDM2011-91 ICD2011-59 pp.103-108 |
| SDM, ICD | 2011-08-26 15:05 |
Toyama | Toyama kenminkaikan | A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue Yuichiro Ishii, Hidehiro Fujiwara, Koji Nii (Renesas Electronics), Hideo Chigasaki, Osamu Kuromiya, Tsukasa Saiki (Renesas Design), Atsushi Miyanishi, Yuji Kihara (Renesas Electronics) SDM2011-92 ICD2011-60 |
We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vddmin). Active bi... [more] | SDM2011-92 ICD2011-60 pp.109-114 |
| SDM, ICD | 2011-08-26 15:30 |
Toyama | Toyama kenminkaikan | A Dynamic body-biased SRAM with Asymmetric Halo Implant MOSFETs Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Koji Maekawa, Motoshige Igarashi, Koji Nii (Renesas) SDM2011-93 ICD2011-61 |
In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design ... [more] | SDM2011-93 ICD2011-61 pp.115-120 |
| ICD | 2009-04-14 10:40 |
Miyagi | Daikanso (Matsushima, Miyagi) | A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2009-6 |
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster a... [more] | ICD2009-6 pp.27-32 |
| ICD | 2009-04-14 11:05 |
Miyagi | Daikanso (Matsushima, Miyagi) | A 7T/14T Dependable SRAM and Its Array Structure to Avoid Half Selection Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST-CREST) ICD2009-7 |
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. The dep... [more] | ICD2009-7 pp.33-38 |
| ICD | 2008-12-12 16:10 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control Kosuke Yamaguchi, Hidehiro Fujiwara, Takashi Takeuchi, Yu Otake, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kove Univ) ICD2008-127 |
We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-... [more] | ICD2008-127 pp.131-136 |
| VLD, IPSJ-SLDM | 2008-05-09 14:35 |
Hyogo | Kobe Univ. | A Dependable SRAM with high-reliability mode and high-speed mode. Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, “quality of a bit （QoB）” for i... [more] | VLD2008-12 pp.31-36 |
| ICD, SDM | 2007-08-24 15:40 |
Hokkaido | Kitami Institute of Technology | An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2007-167 ICD2007-95 |
This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM... [more] | SDM2007-167 ICD2007-95 pp.139-144 |
| ICD, ITE-IST | 2007-07-26 15:40 |
Hyogo | Cross-Layer Design for Low-Power Wireless Sensor Node using Long-Wave Standard Time Code Yu Otake, Masumi Ichien, Takashi Takeuchi, Akihiro Gion, Shinji Mikami, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto (Kobe Univ.) ICD2007-49 |
We propose Isochronous-MAC (I-MAC) using the Long-Wave Standard Time Code, and introduce cross-layer design for a low-po... [more] | ICD2007-49 pp.71-76 |
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| ICD, ITE-IST | 2007-07-26 17:30 |
Hyogo | A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing Shunsuke Okumura, Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-53 |
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten tran... [more] | ICD2007-53 pp.95-100 |
|
| ICD | 2007-04-12 13:50 |
Oita | A Novel Two-Port SRAM for Low Bitline Power Using Majority Logic and Data-Bit Reordering Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-7 |
[more] | ICD2007-7 pp.35-40 |
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