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Committee Date Time Place Paper Title / Authors Abstract Paper #
RCC, MICT 2015-05-28
15:20
Tokyo Kikai-Shinko-Kaikan Bldg Rapid Recovery Technique from Soft Error of FPGAs in Information and Communication Apparatus
Kenichi Shimbo, Tadanobu Toba, Takumi Uezono, Hidefumi Ibe (Hitachi) RCC2015-9 MICT2015-9
As the amount of data traffic through the communication infrastructure is increasing, a development of high-speed inform... [more] RCC2015-9 MICT2015-9
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-02
16:00
Kochi Kochi City Culture-Plaza [Panel Discussion] EMC Circuit Design and Jisso Design for System LSI -- Proposal for Circuit Design Managing EMC and Jisso Issue from Jisso-side --
Hideki Osaka (HITACHI Ltd.), Hideki Asai (Shizuoka Univ.), Hidefumi Ibe (HITACHI Ltd.), Yoshiyuki Saito (Panasonic), Takashi Harada (NEC), Narimasa Takahashi (IBM Japan) CPM2009-142 ICD2009-71
Nowadays, a JISSO design is very important to get the target performance out of a system LSI. More specifically, co-desi... [more] CPM2009-142 ICD2009-71
pp.47-49
ICD, SDM 2008-07-17
15:05
Tokyo Kikai-Shinko-Kaikan Bldg. A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention
Norifumi Kameshiro, Takao Watanabe, Tomoyuki Ishii, Toshiyuki Mine (Hitachi, Ltd.), Toshiaki Sano (Renesas), Hidefumi Ibe, Satoru Akiyama (Hitachi, Ltd.), Kazumasa Yanagisawa, Takashi Ipposhi, Toshiaki Iwamatsu, Yasuhiko Takahashi (Renesas) SDM2008-136 ICD2008-46
We proposed a fully logic compatible process for a single electron shut-off transistor (SESO). A 1-kb memory-cell array ... [more] SDM2008-136 ICD2008-46
pp.47-52
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