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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM, ITE-IST [detail] 2020-08-06
Online Online Over-the-top Si Interposer Embedding Backside Buried Metal to Reduce Power Supply Impedance
Takuji Miki, Makoto Nagata, Akihiro Tsukioka (Kobe Univ.), Noriyuki Miura (Osaka Univ.), Takaaki Okidono (ECSEC), Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi (AIST) SDM2020-5 ICD2020-5
A 2.5D structure with a Si interposer stacked on a CMOS chip is developed to reduce power supply impedance. A backside b... [more] SDM2020-5 ICD2020-5
SDM 2019-02-07
Tokyo   [Invited Talk] Stress Investigation of Annular-Trench-Isolated (ATI) Through Silicon Via (TSV)
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi (AIST) SDM2018-93
The methods as parylene substitute of SiO2 as dielectric layer and annular structure lose efficacy for thermal stress re... [more] SDM2018-93
SDM 2017-02-06
Tokyo Tokyo Univ. [Invited Talk] Development of a Wet Cleaning Process for High-Yield Formation of via-last TSVs
Naoya Watanabe (AIST), Hidekazu Kikuchi, Azusa Yanagisawa (LAPIS), Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi (AIST), Akio Nakamura (LAPIS) SDM2016-145
 [more] SDM2016-145
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