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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| EMM, IT | 2023-05-12 10:40 |
Kyoto | Rakuyu Kaikan (Kyoto Univ. Yoshida-South Campus) (Primary: On-site, Secondary: Online) |
A Study on Synchronization Error Correcting Concatenated Code with Run-Length and Balance Constraints Haruhiko Kaneko (Tokyo Tech)  IT2023-9 EMM2023-9 |
Nonbinary insertion and deletion error correction codes will be effectively applied to DNA storage systems because it of... [more] | IT2023-9 EMM2023-9 pp.43-48 |
| CPSY, DC, IPSJ-ARC [detail] | 2021-07-21 10:15 |
Online | Online | Lossy Error Correction Coding for Vector-Matrix Multiplication Leo Otani, Haruhiko Kaneko (Tokyo Tech) CPSY2021-7 DC2021-7 |
Error control codes are effective to improve the reliability and precision of the vector-matrix multiplications executed... [more] | CPSY2021-7 DC2021-7 pp.37-42 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 18:00 |
Online | Online | A Study on Error Correction Coding For Matrix Multiplications Based On Product Codes Yuki Katsu, Haruhiko Kaneko (Titech) CPSY2020-16 DC2020-16 |
[more] | CPSY2020-16 DC2020-16 pp.99-104 |
| CPSY, DC, IPSJ-ARC [detail] | 2019-07-25 13:55 |
Hokkaido | Kitami Civic Hall | A Study on Multiple-error Correction for Matrix-Product Computation Using Steiner Triple System Yuki Katsu, Haruhiko Kaneko (Tokyo Tech) CPSY2019-26 DC2019-26 |
Improving the reliability of matrix multiplication is a very important factor for the technologies in which matrix multi... [more] | CPSY2019-26 DC2019-26 pp.123-127 |
| WBS, IT, ISEC | 2018-03-09 09:25 |
Tokyo | Katsusika Campas, Tokyo University of Science | A study on segmented deletion error correction using polar code Hikari Koremura, Haruhiko Kaneko (Tokyo Tech) IT2017-126 ISEC2017-114 WBS2017-107 |
While it has been proved that polar code, proposed by Arıkan, achieves the capacity of any discrete memoryless channel, ... [more] | IT2017-126 ISEC2017-114 WBS2017-107 pp.137-141 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-07-26 13:30 |
Akita | Akita Atorion-Building (Akita) | A study on modulation coding for channels with fragmented bit shifts Takeru Hirano, Haruhiko Kaneko (Tokyo Inst. of Tech.) DC2017-16 |
(To be available after the conference date) [more] | DC2017-16 pp.1-6 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2016-08-09 11:45 |
Nagano | Kissei-Bunka-Hall (Matsumoto) | A study on t/m-bit mis-synchronization channel model and error control coding Haruhiko Kaneko (Tokyo Tech) CPSY2016-21 DC2016-18 |
It has been pointed out that high-density storage media, e.g., bit patterned media recording, and high-speed data transf... [more] | CPSY2016-21 DC2016-18 pp.131-138(CPSY), pp.7-14(DC) |
| MRIS, ITE-MMS | 2015-12-10 14:15 |
Ehime | Ehime Univ. | [Invited Talk]
Error correcting codes without markers for deletion-insertion-substitution channels Ryohei Goto, Kenta Kasai, Haruhiko Kaneko (Tokyo Tech.) MR2015-24 |
[more] | MR2015-24 pp.13-18 |
| DC, CPSY (Joint) |
2013-08-01 15:15 |
Fukuoka | Kitakyushu-Kokusai-Kaigijyo | Dependable Data Allocation for Distributed Storage with MDS Code Kousuke Ota, Haruhiko Kaneko (Tokyo Inst. of Tech.) DC2013-16 |
To improve the dependability of disk arrays and distributed storage systems, error control codes are widely adopted, in ... [more] | DC2013-16 pp.1-6 |
| CPSY, DC (Joint) |
2010-08-03 - 2010-08-05 |
Ishikawa | Kanazawa Cultural Hall | Implementaton and evaluation of light weight high speed serial communications with Error Correcting Code Yoshito Sakaguchi, Mochamad Asri, Shinya Takamaeda, Haruhiko Kaneko, Kenji Kise (Tokyo Inst. of Tech.) CPSY2010-19 |
Errror correcting code is required, which is capable enough of correctiong errors, implementable with low resources and... [more] |
CPSY2010-19 pp.67-72 |
| SANE | 2006-04-11 15:10 |
Overseas | Xidian Univ., Xi'an, China | Error Control Coding and Video Compression for Spacecraft Data-Handling Systems Haruhiko Kaneko (JAXA) SANE2006-40 |
Error control coding and data compression are essential techniques for modern high-performance computer systems and high... [more] | SANE2006-40 pp.219-224 |
| SAT | 2006-02-17 14:50 |
Ishikawa | Kanazawa Institute of Technology | Development of Test Circuit for Spotty Byte Error Control Codes Takeshi Sasada, Haruhiko Kaneko (JAXA), Hideki Imashiro (Hitachi-IT) |
Error control coding is essential for semiconductor memory systems used in the space radiation environment because singl... [more] | SAT2005-57 pp.43-48 |
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