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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 09:00 |
Miyazaki |
NewWelCity Miyazaki |
A Circuit Partitioning Strategy for 3-D Integrated Floating-point Multipliers Kazushige Kawai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.) CPM2011-162 ICD2011-94 |
Three-dimensional (3-D) integration technologies are attractive for enhancing the speed of the arithmetic circuits. To i... [more] |
CPM2011-162 ICD2011-94 pp.67-72 |
ICD |
2010-12-17 15:15 |
Tokyo |
RCAST, Univ. of Tokyo |
A Circuit Partitioning Strategy for 3-D Integrated Multipliers Kazuhito Sakai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.) ICD2010-125 |
Three-dimensional(3-D) integration technologies attract a lot of attention to further enhance the performance of the LSI... [more] |
ICD2010-125 pp.153-158 |
ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas |
Ho Chi Minh City University of Technology |
High Performance Hybrid Wave-Pipelined Adder Using A Gain Based Delay Model Truong Thi Kim Tuoi, Jubee Tada, Gensuke Goto (Yamagata Univ.) |
This paper describes a hybrid wave-pipelined adder using a gain based delay model in order to balance the delays in a co... [more] |
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VLD, ICD |
2008-03-07 09:15 |
Okinawa |
TiRuRu |
A delay balancing technique for wave-pipelining Keiichiro Sano, Jubee Tada (Yamagata Univ), Ryusuke Egawa (Touhoku Univ), Gensuke Goto (Yamagata Univ) VLD2007-156 ICD2007-179 |
Wave pipeline is a cutting-edge technology as an alternative to traditional pipeline, However, wave pipelining requires ... [more] |
VLD2007-156 ICD2007-179 pp.1-6 |
ICD, SIP, IE, IPSJ-SLDM |
2006-10-26 11:50 |
Miyagi |
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Reducing the Circuit Size of Multipliers Tan Jiunn Jong Edwin, Ryusuke Egawa (GSIS Tohoku University), Jubee Tada (Faculty of Engineering, Yamagata University), Kenichi Suzuki (GSIS Tohoku University), Gensuke Goto (Faculty of Engineering, Yamagata University), Tadao Nakamura (GSIS Tohoku University) |
Aiming at reducing the power consumption of future VLSIs, a small and fast arithmetic unit is required. Since multiplier... [more] |
SIP2006-91 ICD2006-117 IE2006-69 pp.45-50 |
SIP, ICD, IE, IPSJ-SLDM |
2005-10-21 10:50 |
Miyagi |
Ichinobo, Sakunami-Spa |
Compaction of Arithmetic Unit with Bit-Level-Parallelism Jubee Tada (Yamagata Univ.), Ryusuke Egawa (Tohoku Univ.), Gensuke Goto (Yamagata Univ.), Tadao Nakamura (Tohoku Univ.) |
Aiming at reducing power consumption of VLSIs, we propose a fast and compact arithmetic unit. The arithmetic unit reduc... [more] |
SIP2005-120 ICD2005-139 IE2005-84 pp.31-35 |
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