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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2016-05-11
15:20		 Fukuoka Kitakyushu International Conference Center MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA
Xushen Han, Dajiang Zhou, Shinji Kimura (Waseda Univ.) VLD2016-5		 Convolutional neural network has been paid so much attention in many intelligent applications especially image pattern r... [more] VLD2016-5
pp.47-52
ICD, IPSJ-ARC 2012-01-20
15:50		 Tokyo   A 115mW 1Gbps QC-LDPC Decoder ASIC for WiMAX in 65nm CMOS
Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Dajiang Zhou, Satoshi Goto (Waseda Univ.) ICD2011-143		  [more] ICD2011-143
pp.97-101
IT 2010-09-22
16:10		 Miyagi Tohoku Gakuin University A Low-power and Performance-aware DVB-S2 LDPC Decoder with Layered Scheduling
Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto (Waseda Univ.) IT2010-49		 In this paper we propose an LDPC decoder for DVB-S2 with layered decoding schedule. A particular data updating mechanism... [more] IT2010-49
pp.93-97
IT 2009-09-29
13:35		 Tokyo Sophia Univ. A High-Parallelism Reconfigurable Permutation Network for IEEE 802.11n/802.16e LDPC Decoder
Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto (Waseda Univ.) IT2009-33		 In this paper, we proposed a high-parallelism permutation network (PN) based on Benes network (BN) for LDPC decoder appl... [more] IT2009-33
pp.5-8
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