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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2011-10-20
15:10
Tokyo   An Online Routing Mechanism with Higher Fault-Tolerance for Network-on-Chip
Daihan Wang, Chammika Mannakkara, Vijay Holimath, Tomohiro Yoneda (NII) DC2011-26
In this work we present an idea of a new online fault-tolerant routing mechanism for Network-on-Chip (NoC).
Compared wi... [more]
DC2011-26
pp.37-42
DC, CPSY 2011-04-12
13:50
Tokyo   A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
Chammika Mannakkara, Daihan Wang, Vijay Holimath, Tomohiro Yoneda (NII) CPSY2011-3 DC2011-3
This report presents our first trial to apply a Network-on-Chip (NoC)
architecture to a gasoline engine control, one of... [more]
CPSY2011-3 DC2011-3
pp.11-16
RECONF 2008-05-22
15:40
Fukushima The University of Aizu A Link Removal Methodology for Application-Specific Networks-on-chip on FPGAs
Daihan Wang (Keio Univ./JST), Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII/JST), Hideharu Amano (Keio Univ.) RECONF2008-7
The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic g... [more] RECONF2008-7
pp.37-42
RECONF 2006-09-15
11:45
Kumamoto Kumamoto Univ. A Parametric Study of Packet-Switched FPGA Overlay Networks
Daihan Wang, Hiroki Matsutani, Masato Yoshimi (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
The constantly upgrading gate capacity of FPGAs
enables us to implement a complex system on a chip.
A packet-switched... [more]
RECONF2006-32
pp.31-36
 Results 1 - 4 of 4  /   
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