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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2016-11-11
16:05
Tokyo Kikai-Shinko-Kaikan Bldg. Self-Consistent Device Simulation of a-Si p-i-n Solar Cells and Physical Mechanism of Capture and Emission Processes
Azuma Suzuki (Tsukuba Univ.), Katsuhisa Yoshida (Tokyo Univ.), Nobuyuki Sano (Tsukuba Univ.) SDM2016-89
(To be available after the conference date) [more] SDM2016-89
pp.59-64
ICD 2014-04-18
11:20
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Lecture] A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit
Keiichi Kushida, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Azuma Suzuki, Yusuke Niki, Miyako Shizuno, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba) ICD2014-13
This paper presents a dual-power-supply SRAM that reduces active and stand-by power from room temperature (RT) to high t... [more] ICD2014-13
pp.65-70
ICD 2013-04-12
14:20
Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Lecture] A Power-Reduction Scheme for Dual-Power-Supply SRAM Using BL Power Calculator and Digital LDO
Miyako Shizuno, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba) ICD2013-19
This paper presents a dual-power-supply SRAM that reduces active and stand-by power from room temperature (RT) to high t... [more] ICD2013-19
pp.97-102
ICD 2011-04-19
09:55
Hyogo Kobe University Takigawa Memorial Hall A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers
Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe (Toshiba) ICD2011-9
A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static ... [more] ICD2011-9
pp.49-54
CS, IPSJ-AVM, ITE-BCT, IE [detail] 2010-12-02
10:50
Kyoto Nagoya Univ Free-viewpoint Image Generation using Moving Object Extraction
Kazuma Suzuki (Nagoya Univ.), Norishige Fukushima (Nagoya Inst. Tech.), Tomohiro Yendo, Mehrdad Panahpour Tehrani (Nagoya Univ.), Toshiaki Fujii (Tokyo Inst. Tech.), Masayuki Tanimoto (Nagoya Univ.) CS2010-53 IE2010-92
In this paper, we propose a method of free-viewpoint image generation using moving object extraction. In free-viewpoint ... [more] CS2010-53 IE2010-92
pp.11-16
ICD 2010-04-22
09:00
Kanagawa Shonan Institute of Tech. [Invited Talk] A Configurable SRAM with Constant-Negative-Level Write Buffer for Low Voltage Operation with 0.149μm2 Cell in 32nm High-k Metal Gate CMOS
Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe (Toshiba Corp.) ICD2010-1
This paper presents a configurable SRAM for low voltage operation with Constant-Negative-Level Write Buffer (CNL-WB) and... [more] ICD2010-1
pp.1-6
ICD 2009-04-14
10:15
Miyagi Daikanso (Matsushima, Miyagi) A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179μm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver
Yuki Fujimura, Osamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe (Toshiba Co.) ICD2009-5
We present a dual-power-supply SRAM with 0.179$\mu$m2 cell in 40nm CMOS, which is 10% smaller than the SRAM scaling tren... [more] ICD2009-5
pp.21-26
 Results 1 - 7 of 7  /   
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